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mb/google/kohaku: Update DPTF parameters and TCC offset setting 

This change applies fine-tuned DPTF parameters and TCC offset setting
for kohaku. Also enables EC_ENABLE_MULTIPLE_DPTF_PROFILES for tablet
mode.

BUG=b:137688474
BRANCH=none
TEST=built and verified the setting values

Change-Id: I92e268b2e07ca5a04e29bda84ddb8fc21eb23251
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35532
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
This commit is contained in:
Seunghwan Kim 2019-09-23 10:19:17 +09:00 committed by Patrick Georgi
parent 9400f84d31
commit df02f7aed8
3 changed files with 27 additions and 15 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

38
src/mainboard/google/hatch/variants/kohaku/include/variant/acpi/dptf.asl
View File

@ -13,28 +13,36 @@
* GNU General Public License for more details.
*/
#define DPTF_CPU_PASSIVE 95
#define DPTF_CPU_PASSIVE 50
#define DPTF_CPU_CRITICAL 105
#define DPTF_TSR0_SENSOR_ID 0
#define DPTF_TSR0_SENSOR_NAME "Thermal Sensor - Charger"
#define DPTF_TSR0_PASSIVE 49
#define DPTF_TSR0_CRITICAL 75
#define DPTF_TSR0_PASSIVE 45
#define DPTF_TSR0_CRITICAL 90
#define DPTF_TSR0_TABLET_PASSIVE 32
#define DPTF_TSR0_TABLET_CRITICAL 90
#define DPTF_TSR1_SENSOR_ID 1
#define DPTF_TSR1_SENSOR_NAME "Thermal Sensor - 5V"
#define DPTF_TSR1_PASSIVE 65
#define DPTF_TSR1_CRITICAL 75
#define DPTF_TSR1_PASSIVE 45
#define DPTF_TSR1_CRITICAL 90
#define DPTF_TSR1_TABLET_PASSIVE 32
#define DPTF_TSR1_TABLET_CRITICAL 90
#define DPTF_TSR2_SENSOR_ID 2
#define DPTF_TSR2_SENSOR_NAME "Thermal Sensor - IA"
#define DPTF_TSR2_PASSIVE 65
#define DPTF_TSR2_CRITICAL 75
#define DPTF_TSR2_PASSIVE 45
#define DPTF_TSR2_CRITICAL 90
#define DPTF_TSR2_TABLET_PASSIVE 32
#define DPTF_TSR2_TABLET_CRITICAL 90
#define DPTF_TSR3_SENSOR_ID 3
#define DPTF_TSR3_SENSOR_NAME "Thermal Sensor - GT"
#define DPTF_TSR3_PASSIVE 65
#define DPTF_TSR3_CRITICAL 75
#define DPTF_TSR3_PASSIVE 45
#define DPTF_TSR3_CRITICAL 90
#define DPTF_TSR3_TABLET_PASSIVE 32
#define DPTF_TSR3_TABLET_CRITICAL 90
#define DPTF_ENABLE_CHARGER
@ -48,19 +56,19 @@ Name (CHPS, Package () {
Name (DTRT, Package () {
/* CPU Throttle Effect on CPU */
Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 100, 50, 0, 0, 0, 0 },
Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 100, 10, 0, 0, 0, 0 },
/* CPU Throttle Effect on 5V (TSR1) */
Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 100, 60, 0, 0, 0, 0 },
Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 100, 10, 0, 0, 0, 0 },
/* Charger Throttle Effect on Charger (TSR0) */
Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR0, 100, 94, 0, 0, 0, 0 },
/* CPU Throttle Effect on IA (TSR2) */
Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR2, 100, 60, 0, 0, 0, 0 },
Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR2, 100, 10, 0, 0, 0, 0 },
/* CPU Throttle Effect on GT (TSR3) */
Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR3, 100, 60, 0, 0, 0, 0 },
Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR3, 100, 10, 0, 0, 0, 0 },
})
Name (MPPC, Package ()
@ -68,8 +76,8 @@ Name (MPPC, Package ()
0x2, /* Revision */
Package () { /* Power Limit 1 */
0, /* PowerLimitIndex, 0 for Power Limit 1 */
8000, /* PowerLimitMinimum */
15000, /* PowerLimitMaximum */
7000, /* PowerLimitMinimum */
9000, /* PowerLimitMaximum */
28000, /* TimeWindowMinimum */
28000, /* TimeWindowMaximum */
250 /* StepSize */

2
src/mainboard/google/hatch/variants/kohaku/include/variant/ec.h
View File

@ -18,4 +18,6 @@
#include <baseboard/ec.h>
#define EC_ENABLE_MULTIPLE_DPTF_PROFILES
#endif

2
src/mainboard/google/hatch/variants/kohaku/overridetree.cb
View File

@ -2,6 +2,8 @@ chip soc/intel/cannonlake
register "tdp_pl1_override" = "8"
register "tdp_pl2_override" = "51"
register "tcc_offset" = "35" # TCC of 65C
register "SerialIoDevMode" = "{
[PchSerialIoIndexI2C0] = PchSerialIoPci,
[PchSerialIoIndexI2C1] = PchSerialIoPci,