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soc/intel/alderlake: Add handling of GPIO_COM3 in gpio.asl 

We were not adding power management handling of GPIO_COM3 in gpio.asl
This can affect s0ix flow where platform won't go into s0ix since
GPIO_COM3 is not power gated.

BUG=b:188392183
BRANCH=None
TEST=Platform should enter to s0ix and GPIO COMM3 should not block an
entry to s0ix.

Change-Id: I3f269c66bdd6337adb0d2bd29d0b7d72ced19ec4
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54391
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Maulik V Vaghela 2021-05-17 19:50:54 +05:30 committed by Tim Wawrzynczak
parent a77eb6e6c3
commit df092c1ded
1 changed files with 10 additions and 1 deletions
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11
src/soc/intel/alderlake/acpi/gpio.asl
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@ -80,6 +80,12 @@ Method (GADD, 1, NotSerialized)
Local0 = PID_GPIOCOM2 Local0 = PID_GPIOCOM2
Local1 = Arg0 - GPIO_COM2_START Local1 = Arg0 - GPIO_COM2_START
} }
/* GPIO Community 3 */
If (Arg0 >= GPIO_COM3_START && Arg0 <= GPIO_COM3_END)
{
Local0 = PID_GPIOCOM3
Local1 = Arg0 - GPIO_COM3_START
}
/* GPIO Community 4 */ /* GPIO Community 4 */
If (Arg0 >= GPIO_COM4_START && Arg0 <= GPIO_COM4_END) If (Arg0 >= GPIO_COM4_START && Arg0 <= GPIO_COM4_END)
{ {
@ -115,6 +121,9 @@ Method (GPID, 1, Serialized)
Case (COMM_2) { Case (COMM_2) {
Local0 = PID_GPIOCOM2 Local0 = PID_GPIOCOM2
} }
case (COMM_3) {
Local0 = PID_GPIOCOM3
}
Case (COMM_4) { Case (COMM_4) {
Local0 = PID_GPIOCOM4 Local0 = PID_GPIOCOM4
} }
@ -130,7 +139,7 @@ Method (GPID, 1, Serialized)
} }
/* GPIO Power Management bits */ /* GPIO Power Management bits */
Name(GPMB, Package(TOTAL_GPIO_COMM) {0, 0, 0, 0, 0}) Name(GPMB, Package(TOTAL_GPIO_COMM) {0, 0, 0, 0, 0, 0})
/* /*
* Save GPIO Power Management bits * Save GPIO Power Management bits