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Maulik V Vaghela df092c1ded soc/intel/alderlake: Add handling of GPIO_COM3 in gpio.asl
We were not adding power management handling of GPIO_COM3 in gpio.asl
This can affect s0ix flow where platform won't go into s0ix since
GPIO_COM3 is not power gated.

BUG=b:188392183
BRANCH=None
TEST=Platform should enter to s0ix and GPIO COMM3 should not block an
entry to s0ix.

Change-Id: I3f269c66bdd6337adb0d2bd29d0b7d72ced19ec4
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54391
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-05-18 17:03:43 +00:00
3rdparty Update vboot submodule to upstream/main (e681c37) 2021-05-16 21:53:53 +00:00
Documentation Documentation/gerrit: Describe core developer responsibilities 2021-05-17 22:20:44 +00:00
LICENSES
configs cpu/x86/smm: Drop the V1 smmloader 2021-04-19 06:36:28 +00:00
payloads payload/tianocore: Drop TIANOCORE_TARGET_IA32 2021-05-18 10:04:47 +00:00
src soc/intel/alderlake: Add handling of GPIO_COM3 in gpio.asl 2021-05-18 17:03:43 +00:00
tests tests/lib/spd_cache-test: Initialize spd_block.addr_map 2021-05-18 10:08:39 +00:00
util util/testing/Makefile.inc: Add new line as help section separator 2021-05-18 10:09:59 +00:00
.checkpatch.conf lint: checkpatch: Only exclude specific src/vendorcode/ subdirectories 2021-04-06 16:04:41 +00:00
.clang-format
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.gitmodules .gitmodules: update vboot submodule to track branch=main 2021-04-28 16:33:07 +00:00
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MAINTAINERS mb/asus/p8h61-m_pro: Transform into variant setup 2021-05-18 11:50:02 +00:00
Makefile Makefile: Don't run genbuild_h if not doing a build 2021-05-12 15:13:39 +00:00
Makefile.inc option: Introduce `CMOS_LAYOUT_FILE` Kconfig symbol 2021-05-18 11:43:49 +00:00
README.md
gnat.adc
toolchain.inc toolchain.inc: Update and fix the test-toolchain target 2021-02-24 11:29:39 +00:00

README.md

coreboot README

coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.

With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.

coreboot was formerly known as LinuxBIOS.

Payloads

After the basic initialization of the hardware has been performed, any desired "payload" can be started by coreboot.

See https://www.coreboot.org/Payloads for a list of supported payloads.

Supported Hardware

coreboot supports a wide range of chipsets, devices, and mainboards.

For details please consult:

Build Requirements

  • make
  • gcc / g++ Because Linux distribution compilers tend to use lots of patches. coreboot does lots of "unusual" things in its build system, some of which break due to those patches, sometimes by gcc aborting, sometimes - and that's worse - by generating broken object code. Two options: use our toolchain (eg. make crosstools-i386) or enable the ANY_TOOLCHAIN Kconfig option if you're feeling lucky (no support in this case).
  • iasl (for targets with ACPI support)
  • pkg-config
  • libssl-dev (openssl)

Optional:

  • doxygen (for generating/viewing documentation)
  • gdb (for better debugging facilities on some targets)
  • ncurses (for make menuconfig and make nconfig)
  • flex and bison (for regenerating parsers)

Building coreboot

Please consult https://www.coreboot.org/Build_HOWTO for details.

Testing coreboot Without Modifying Your Hardware

If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.

Please see https://www.coreboot.org/QEMU for details.

Website and Mailing List

Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:

https://www.coreboot.org

You can contact us directly on the coreboot mailing list:

https://www.coreboot.org/Mailinglist

The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.

coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the "GPL (version 2, or any later version)", and some files are licensed under the "GPL, version 2". For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.

This makes the resulting coreboot images licensed under the GPL, version 2.