soc/intel/apollolake: Update FSP Header files for version 146_30
Add new UPDs for Fspm and Fsps. Update headers to make new UPDs available for use. New UPDs enable various memory and trace funtionality options as well as support for zero sized IBB region. BUG=chrome-os-partner:55513 BRANCH=none TEST=built and tested with no regressions Change-Id: Id1573baaa306ed4fe4353df5f27e5963cb1a76e6 Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com> Reviewed-on: https://review.coreboot.org/15815 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This commit is contained in:
Brandon Breitenstein
Stefan Reinauer
parent
fde3275fb4
commit
df12d1923f
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@ -571,9 +571,86 @@ struct FSP_M_CONFIG {
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**/
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uint8_t SkipCseRbp;
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/** Offset 0x0136
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/** Offset 0x0136 - Npk Enable
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Enable/Disable Npk. 0:Disable, 1:Enable, 2:Debugger, 3:Auto(Default).
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0:Disable, 1:Enable, 2:Debugger, 3:Auto
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**/
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uint8_t ReservedFspmUpd[26];
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uint8_t NpkEn;
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/** Offset 0x0137 - FW Trace Enable
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Enable/Disable FW Trace. 0:Disable, 1:Enable(Default).
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$EN_DIS
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**/
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uint8_t FwTraceEn;
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/** Offset 0x0138 - FW Trace Destination
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FW Trace Destination. 1-NPK_TRACE_TO_MEMORY, 2-NPK_TRACE_TO_DCI, 3-NPK_TRACE_TO_BSSB,
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4-NPK_TRACE_TO_PTI(Default).
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**/
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uint8_t FwTraceDestination;
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/** Offset 0x0139 - NPK Recovery Dump
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Enable/Disable NPK Recovery Dump. 0:Disable(Default), 1:Enable.
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$EN_DIS
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**/
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uint8_t RecoverDump;
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/** Offset 0x013A - Memory Region 0 Buffer Size
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Memory Region 0 Buffer Size. 0-0MB(Default), 1-1MB, 2-8MB, 3-64MB, 4-128MB, 5-256MB,
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6-512MB, 7-1GB.
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**/
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uint32_t Msc0Size;
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/** Offset 0x013E - Memory Region 0 Buffer WrapAround
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Memory Region 0 Buffer WrapAround. 0-n0-warp, 1-warp(Default).
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**/
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uint8_t Msc0Wrap;
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/** Offset 0x013F - Memory Region 1 Buffer Size
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Memory Region 1 Buffer Size, 0-0MB(Default), 1-1MB, 2-8MB, 3-64MB, 4-128MB, 5-256MB,
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6-512MB, 7-1GB.
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**/
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uint32_t Msc1Size;
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/** Offset 0x0143 - Memory Region 1 Buffer WrapAround
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Memory Region 1 Buffer WrapAround. 0-n0-warp, 1-warp(Default).
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**/
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uint8_t Msc1Wrap;
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/** Offset 0x0144 - PTI Mode
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PTI Mode. 0-0ff, 1-x4(Default), 2-x8, 3-x12, 4-x16.
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**/
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uint8_t PtiMode;
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/** Offset 0x0145 - PTI Training
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PTI Training. 0-off(Default), 1-6=1-6.
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**/
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uint8_t PtiTraining;
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/** Offset 0x0146 - PTI Speed
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PTI Speed. 0-full, 1-half, 2-quarter(Default).
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**/
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uint8_t PtiSpeed;
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/** Offset 0x0147 - Punit Message Level
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Punit Message Output Verbosity Level. 0, 1(Default), 2-4=2-4.
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**/
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uint8_t PunitMlvl;
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/** Offset 0x0148 - PMC Message Level
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PMC Message Output Verbosity Level. 0, 1(Default), 2-4=2-4.
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**/
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uint8_t PmcMlvl;
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/** Offset 0x0149 - SW Trace Enable
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Enable/Disable SW Trace. 0:Disable(Default), 1:Enable.
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$EN_DIS
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**/
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uint8_t SwTraceEn;
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/** Offset 0x014A
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**/
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uint8_t ReservedFspmUpd[6];
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} __attribute__((packed));
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/** Fsp M Test Configuration
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@ -71,7 +71,7 @@ struct FSP_S_CONFIG {
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/** Offset 0x0025 - Memory region allocation for Processor Trace
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Memory region allocation for Processor Trace, allowed range is from 4K (0x0) to
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128MB (0xF); 0xFF: Disable. 0xFF:Disable(Default)
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128MB (0xF); <b>0xFF: Disable. 0xFF:Disable(Default)
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**/
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uint8_t ProcTraceMemSize;
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@ -440,7 +440,7 @@ struct FSP_S_CONFIG {
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uint8_t Pme;
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/** Offset 0x0091 - HD-Audio I/O Buffer Ownership
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Set HD-Audio I/O Buffer Ownership. 0:Disable(Default), 1:Enable.
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Set HD-Audio I/O Buffer Ownership. 0:HD-Audio link owns all the I/O buffers(Default)
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0:HD-Audio link owns all the I/O buffers, 1:HD-Audio link owns 4 I/O buffers and
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I2S port owns 4 I/O buffers, 3:I2S port owns all the I/O buffers
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**/
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@ -788,7 +788,7 @@ struct FSP_S_CONFIG {
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/** Offset 0x00E4 - Enable PCIE Clock Gating
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Enable/disable PCIE Clock Gating. 0:Enable, 1:Disable(Default).
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$EN_DIS
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0:Enable, 1:Disable
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**/
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uint8_t PcieClockGatingDisabled;
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@ -1334,13 +1334,13 @@ struct FSP_S_CONFIG {
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/** Offset 0x02D2 - Skip Multi-Processor Initialization
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When this is skipped, boot loader must initialize processors before SilicionInit
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API. 0: Initialize(Default), 1: Skip
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API. 0: Initialize(Default), <b>1: Skip
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$EN_DIS
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**/
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uint8_t SkipMpInit;
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/** Offset 0x02D3 - DCI Auto Detect
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Enable/disable DCI AUTO mode.
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Enable/disable DCI AUTO mode. Enabled(Default).
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$EN_DIS
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**/
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uint8_t DciAutoDetect;
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@ -1467,11 +1467,9 @@ struct FSP_S_CONFIG {
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**/
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uint8_t PcieRpSelectableDeemphasis[6];
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/** Offset 0x0326 - Os Selection Mode
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Select OS mode. 0:Windows(default), 1:Android, 2:Win7
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0:Windows, 1:Android, 2:Win7
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/** Offset 0x0326
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**/
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uint8_t OsSelection;
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uint8_t UnusedUpdSpace4;
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/** Offset 0x0327 - Monitor Mwait Enable
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Enable/Disable Monitor Mwait. For Windows* OS, this should be Enabled. For Linux
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