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nb/amd/amdmct/mct_ddr3: Fix a minor RDIMM CS select error 

Change-Id: I4cdfeec887813c17edcdee8858222414fb19b72c
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12057
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Timothy Pearson 2015-08-27 13:18:53 -05:00 committed by Martin Roth
parent 0eb163d5d3
commit df499b53c3
1 changed files with 2 additions and 2 deletions
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4
src/northbridge/amd/amdmct/mct_ddr3/mctrci.c
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@ -232,7 +232,7 @@ void mct_DramControlReg_Init_D(struct MCTStatStruc *pMCTstat,
for (MrsChipSel = 0; MrsChipSel < 8; MrsChipSel ++, MrsChipSel ++) { for (MrsChipSel = 0; MrsChipSel < 8; MrsChipSel ++, MrsChipSel ++) {
if (pDCTstat->CSPresent & (1 << MrsChipSel)) { if (pDCTstat->CSPresent & (1 << MrsChipSel)) {
val = Get_NB32_DCT(dev, dct, 0xa8); val = Get_NB32_DCT(dev, dct, 0xa8);
val &= ~(0xf << 8); val &= ~(0xff << 8);
switch (MrsChipSel) { switch (MrsChipSel) {
case 0: case 0:
@ -279,7 +279,7 @@ void FreqChgCtrlWrd(struct MCTStatStruc *pMCTstat,
/* 2. Program F2x[1, 0]A8[CtrlWordCS]=bit mask for target chip selects. */ /* 2. Program F2x[1, 0]A8[CtrlWordCS]=bit mask for target chip selects. */
val = Get_NB32_DCT(dev, dct, 0xa8); val = Get_NB32_DCT(dev, dct, 0xa8);
val &= ~(0xff << 8); val &= ~(0xff << 8);
val |= (0x3 << (MrsChipSel & 0xfe)) << 8; val |= (0x3 << (MrsChipSel & ~0x1)) << 8;
Set_NB32_DCT(dev, dct, 0xa8, val); Set_NB32_DCT(dev, dct, 0xa8, val);
/* Resend control word 10 */ /* Resend control word 10 */