soc/intel/jsl: Add disable_external_bypass_vr config

This dev tree config controls the Vnn/Vcc1P05 bypass mode for Jasperlake.

BUG=b:191691430
BRANCH=dedede
TEST=Build fw and confirm FSP setting are set properly by log

Signed-off-by: Simon Yang <simon1.yang@intel.com>
Change-Id: I10bc203d3fed32ab65f325978426b7d0fca6f392
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55744
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jamie Chen <jamie.chen@intel.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>

src/soc/intel/jasperlake/chip.h

@@ -403,6 +403,18 @@ struct soc_intel_jasperlake_config {
 	 */
 	uint8_t RampDown;
 
+	/*
+	 * It controls below soc variables
+	 *
+	 *   PchFivrExtV1p05RailEnabledStates
+	 *   PchFivrExtVnnRailSxEnabledStates
+	 *   PchFivrExtVnnRailEnabledStates
+	 *
+	 * If your platform does not support external vnn power rail please set to 1
+	 * 1: Disabled ; 0: Enabled
+	 */
+	bool disable_external_bypass_vr;
+
 };
 
 typedef struct soc_intel_jasperlake_config config_t;

src/soc/intel/jasperlake/fsp_params.c

@@ -196,6 +196,12 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 		params->RampDown = config->RampDown;
 	}
 
+	if (config->disable_external_bypass_vr) {
+		params->PchFivrExtV1p05RailEnabledStates = 0;
+		params->PchFivrExtVnnRailSxEnabledStates = 0;
+		params->PchFivrExtVnnRailEnabledStates = 0;
+	}
+
 	/* Override/Fill FSP Silicon Param for mainboard */
 	mainboard_silicon_init_params(params);
 }