src: Add missing include <stdint.h>

Change-Id: I6a9d71e69ed9230b92f0f330875515a5df29fc06
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29312
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/arch/riscv/include/arch/pmp.h

@@ -16,6 +16,8 @@
 #ifndef __RISCV_PMP_H__
 #define __RISCV_PMP_H__
 
+#include <stdint.h>
+
 /*
  * this function needs to be implemented by a specific SoC.
  * return number of PMP entries for current hart

src/cpu/intel/model_206ax/model_206ax.h

@@ -17,6 +17,8 @@
 #ifndef _CPU_INTEL_MODEL_206AX_H
 #define _CPU_INTEL_MODEL_206AX_H
 
+#include <stdint.h>
+
 /* SandyBridge/IvyBridge bus clock is fixed at 100MHz */
 #define SANDYBRIDGE_BCLK		100
 

src/include/cpu/amd/multicore.h

@@ -16,6 +16,8 @@
 #ifndef CPU_AMD_QUADCORE_H
 #define CPU_AMD_QUADCORE_H
 
+#include <stdint.h>
+
 u32 read_nb_cfg_54(void);
 
 struct node_core_id {

src/include/pc80/keyboard.h

@@ -1,6 +1,8 @@
 #ifndef PC80_KEYBOARD_H
 #define PC80_KEYBOARD_H
 
+#include <stdint.h>
+
 #define NO_AUX_DEVICE		0
 #define PROBE_AUX_DEVICE	1
 

src/mainboard/google/rambi/variants/banjo/include/variant/variant.h

@@ -14,6 +14,8 @@
 #ifndef VARIANT_H
 #define VARIANT_H
 
+#include <stdint.h>
+
 /*
  * RAM_ID[2:0] are on GPIO_SSUS[39:37]
  * 0b000 - 2GiB total - 1 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz

src/mainboard/google/rambi/variants/candy/include/variant/variant.h

@@ -14,6 +14,8 @@
 #ifndef VARIANT_H
 #define VARIANT_H
 
+#include <stdint.h>
+
 /*
  * RAM_ID[3:0] are on GPIO_SSUS[40:37]
  * 0b0000 - 4GiB total - 2 x 2GiB Micron MT41K256M16HA-125:E 1600MHz

src/mainboard/google/rambi/variants/clapper/include/variant/variant.h

@@ -14,6 +14,8 @@
 #ifndef VARIANT_H
 #define VARIANT_H
 
+#include <stdint.h>
+
 /*
  * RAM_ID[2:0] are on GPIO_SSUS[39:37]
  * 0b000 - 4GiB total - 2 x 2GiB Micron MT41K256M16HA-125:E 1600MHz

src/mainboard/google/rambi/variants/enguarde/include/variant/variant.h

@@ -14,6 +14,8 @@
 #ifndef VARIANT_H
 #define VARIANT_H
 
+#include <stdint.h>
+
 /*
  * RAM_ID[2:0] are on GPIO_SSUS[39:37]
  * 0b000 - 4GiB total - 2 x 2GiB Micron MT41K256M16HA-125:E 1600MHz

src/mainboard/google/rambi/variants/glimmer/include/variant/variant.h

@@ -14,6 +14,8 @@
 #ifndef VARIANT_H
 #define VARIANT_H
 
+#include <stdint.h>
+
 /*
  * RAM_ID[2:0] are on GPIO_SSUS[39:37]
  * 0b0000 - 4GiB total - 2 x 2GiB Micron  MT41K256M16HA-125:E 1600MHz

src/mainboard/google/rambi/variants/gnawty/include/variant/variant.h

@@ -14,6 +14,8 @@
 #ifndef VARIANT_H
 #define VARIANT_H
 
+#include <stdint.h>
+
 /*
  * RAM_ID[2:0] are on GPIO_SSUS[39:37]
  * 0b000 - 4GiB total - 2 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz

src/mainboard/google/rambi/variants/heli/include/variant/variant.h

@@ -14,6 +14,8 @@
 #ifndef VARIANT_H
 #define VARIANT_H
 
+#include <stdint.h>
+
 /*
  * RAM_ID[3:0] are on GPIO_SSUS[40:37]
  * RAM_ID	Vendor	Vendor_PN	Freq	Size	Total_size	channel

src/mainboard/google/rambi/variants/kip/include/variant/variant.h

@@ -14,6 +14,8 @@
 #ifndef VARIANT_H
 #define VARIANT_H
 
+#include <stdint.h>
+
 /*
  * RAM_ID[2:0] are on GPIO_SSUS[39:37]
  * 0b000 - 4GiB total - 2 x 2GiB Micron  MT41K256M16HA-125:E 1600MHz

src/mainboard/google/rambi/variants/ninja/include/variant/variant.h

@@ -14,6 +14,8 @@
 #ifndef VARIANT_H
 #define VARIANT_H
 
+#include <stdint.h>
+
 /*
  * RAM_ID[2:0] are on GPIO_SSUS[39:37]
  * 0b000 - 4GiB total - 2 x 2GiB Micron MT41K256M16HA-125:E 1600MHz

src/mainboard/google/rambi/variants/orco/include/variant/variant.h

@@ -14,6 +14,8 @@
 #ifndef VARIANT_H
 #define VARIANT_H
 
+#include <stdint.h>
+
 /*
  * RAM_ID[2:0] are on GPIO_SSUS[39:37]
  * 0b000 - 4GiB total - 2 x 2GiB Micron MT41K256M16HA-125:E 1600MHz

src/mainboard/google/rambi/variants/quawks/include/variant/variant.h

@@ -14,6 +14,8 @@
 #ifndef VARIANT_H
 #define VARIANT_H
 
+#include <stdint.h>
+
 /*
  * RAM_ID[2:0] are on GPIO_SSUS[39:37]
  * 0b000 - 4GiB total - 2 x 2GiB Elpida EDJ4216EFBG-GNL-F 1600MHz

src/mainboard/google/rambi/variants/rambi/include/variant/variant.h

@@ -14,6 +14,8 @@
 #ifndef VARIANT_H
 #define VARIANT_H
 
+#include <stdint.h>
+
 /*
  * RAM_ID[2:0] are on GPIO_SSUS[39:37]
  * 0b000 - 4GiB total - 2 x 2GiB Micron MT41K256M16HA-125:E 1600MHz

src/mainboard/google/rambi/variants/squawks/include/variant/variant.h

@@ -14,6 +14,8 @@
 #ifndef VARIANT_H
 #define VARIANT_H
 
+#include <stdint.h>
+
 /*
  * RAM_ID[2:0] are on GPIO_SSUS[39:37]
  * 0b000 - 4GiB total - 2 x 2GiB Elpida EDJ4216EFBG-GNL-F 1600MHz

src/mainboard/google/rambi/variants/sumo/include/variant/variant.h

@@ -14,6 +14,8 @@
 #ifndef VARIANT_H
 #define VARIANT_H
 
+#include <stdint.h>
+
 /*
  * RAM_ID[2:0] are on GPIO_SSUS[39:37]
  * 0b000 - 4GiB total - 2 x 2GiB Micron MT41K256M16HA-125:E 1600MHz

src/mainboard/google/rambi/variants/swanky/include/variant/variant.h

@@ -14,6 +14,8 @@
 #ifndef VARIANT_H
 #define VARIANT_H
 
+#include <stdint.h>
+
 /*
  * RAM_ID[2:0] are on GPIO_SSUS[39:37]
  * 0b000 - 2GiB total - 1 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz

src/mainboard/google/rambi/variants/winky/include/variant/variant.h

@@ -14,6 +14,8 @@
 #ifndef VARIANT_H
 #define VARIANT_H
 
+#include <stdint.h>
+
 /*
  * RAM_ID[2:0] are on GPIO_SSUS[39:37]
  * 0b000 - 4GiB total - 2 x 2GiB Micron MT41K256M16HA-125:E 1600MHz

src/mainboard/google/smaug/pmic.h

@@ -17,6 +17,8 @@
 #ifndef __MAINBOARD_GOOGLE_FOSTER_PMIC_H__
 #define __MAINBOARD_GOOGLE_FOSTER_PMIC_H__
 
+#include <stdint.h>
+
 #define MAX77620_SD0_REG		0x16
 #define MAX77620_SD1_REG		0x17
 #define MAX77620_SD2_REG		0x18

src/mainboard/intel/harcuvar/spd/spd.h

@@ -18,6 +18,8 @@
 #ifndef MAINBOARD_SPD_H
 #define MAINBOARD_SPD_H
 
+#include <stdint.h>
+
 #define SPD_LEN 512
 
 #define SPD_DRAM_TYPE 2

src/northbridge/amd/amdmct/mct/mct.h

@@ -16,6 +16,9 @@
 
 #ifndef MCT_H
 #define MCT_H
+
+#include <stdint.h>
+
 /*===========================================================================
 	CPU - K8/FAM10
 ===========================================================================*/

src/northbridge/amd/lx/raminit.h

@@ -17,6 +17,8 @@
 #ifndef RAMINIT_H
 #define RAMINIT_H
 
+#include <stdint.h>
+
 #define DIMM_SOCKETS 2
 
 struct mem_controller {

src/security/tpm/tss/common/tss_common.h

@@ -17,6 +17,8 @@
 #ifndef TCG_TSS_COMMON_H_
 #define TCG_TSS_COMMON_H_
 
+#include <stdint.h>
+
 #define TPM_PCR_MINIMUM_DIGEST_SIZE 20
 #define TPM_SUCCESS ((uint32_t)0x00000000)
 

src/soc/intel/apollolake/include/soc/heci.h

@@ -17,6 +17,8 @@
 #ifndef _SOC_APOLLOLAKE_HECI_H_
 #define _SOC_APOLLOLAKE_HECI_H_
 
+#include <stdint.h>
+
 enum sec_status {
 	SEC_STATE_RESET = 0,
 	SEC_STATE_INIT,

src/soc/intel/baytrail/include/soc/iomap.h

@@ -16,7 +16,6 @@
 #ifndef _BAYTRAIL_IOMAP_H_
 #define _BAYTRAIL_IOMAP_H_
 
-
 /*
  * Memory Mapped IO bases.
  */
@@ -79,6 +78,8 @@
 #define SMBUS_BASE_ADDRESS		0xefa0
 
 #ifndef __ACPI__
+#include <stdint.h>
+
 /* Read Top of Low Memory (BMBOUND) */
 uint32_t nc_read_top_of_low_memory(void);
 #endif

src/soc/intel/braswell/include/soc/iomap.h

@@ -17,7 +17,6 @@
 #ifndef _SOC_IOMAP_H_
 #define _SOC_IOMAP_H_
 
-
 /*
  * Memory Mapped IO bases.
  */
@@ -81,6 +80,8 @@
 #define SMBUS_BASE_ADDRESS		0xefa0
 
 #ifndef __ACPI__
+#include <stdint.h>
+
 /* Read Top of Low Memory (BMBOUND) */
 uint32_t nc_read_top_of_low_memory(void);
 #endif

src/soc/intel/cannonlake/include/soc/lpc.h

@@ -17,6 +17,8 @@
 #ifndef _SOC_CANNONLAKE_LPC_H_
 #define _SOC_CANNONLAKE_LPC_H_
 
+#include <stdint.h>
+
 /* PCI Configuration Space (D31:F0): LPC */
 #define SCI_IRQ_SEL		(7 << 0)
 #define SCIS_IRQ9		0

src/soc/intel/common/block/include/intelblocks/smm.h

@@ -17,6 +17,8 @@
 #ifndef SOC_INTEL_COMMON_BLOCK_SMM_H
 #define SOC_INTEL_COMMON_BLOCK_SMM_H
 
+#include <stdint.h>
+
 /*
  * This common code block relies on each specific SOC defining the macro
  * ENABLE_SMI_PARAMS for the values needed for SMI enabling on the

src/soc/intel/common/block/include/intelblocks/vmx.h

@@ -14,6 +14,8 @@
 #ifndef SOC_INTEL_COMMON_BLOCK_VMX_H
 #define SOC_INTEL_COMMON_BLOCK_VMX_H
 
+#include <stdint.h>
+
 struct vmx_param {
 	uint8_t enable;
 };

src/soc/intel/fsp_baytrail/include/soc/iomap.h

@@ -16,7 +16,6 @@
 #ifndef _BAYTRAIL_IOMAP_H_
 #define _BAYTRAIL_IOMAP_H_
 
-
 /*
  * Memory Mapped IO bases.
  */
@@ -79,6 +78,8 @@
 #define SMBUS_BASE_ADDRESS		0xefa0
 
 #ifndef __ACPI__
+#include <stdint.h>
+
 /* Read Top of Low Memory (BMBOUND) */
 uint32_t nc_read_top_of_low_memory(void);
 #endif

src/soc/intel/icelake/include/soc/lpc.h

@@ -16,6 +16,8 @@
 #ifndef _SOC_ICELAKE_LPC_H_
 #define _SOC_ICELAKE_LPC_H_
 
+#include <stdint.h>
+
 /* PCI Configuration Space (D31:F0): LPC */
 #define SCI_IRQ_SEL		(7 << 0)
 #define SCIS_IRQ9		0

src/soc/mediatek/mt8173/include/soc/da9212.h

@@ -16,6 +16,8 @@
 #ifndef __SOC_DA9212_H_
 #define __SOC_DA9212_H_
 
+#include <stdint.h>
+
 void da9212_probe(uint8_t i2c_num);
 
 enum {

src/soc/mediatek/mt8173/include/soc/mt6311.h

@@ -16,6 +16,8 @@
 #ifndef __SOC_MEDIATEK_MT8173_MT6311_H__
 #define __SOC_MEDIATEK_MT8173_MT6311_H__
 
+#include <stdint.h>
+
 void mt6311_probe(uint8_t i2c_num);
 
 enum {

src/soc/qualcomm/ipq40xx/include/soc/ebi2.h

@@ -31,6 +31,8 @@
 #ifndef __SOC_QUALCOMM_IPQ40XX_EBI2_H_
 #define __SOC_QUALCOMM_IPQ40XX_EBI2_H_
 
+#include <stdint.h>
+
 #define EBI2CR_BASE                                       (0x1A600000)
 
 struct ebi2cr_regs {

src/soc/rockchip/rk3399/include/soc/tsadc.h

@@ -16,6 +16,8 @@
 #ifndef __SOC_ROCKCHIP_RK3399_TSADC_H__
 #define __SOC_ROCKCHIP_RK3399_TSADC_H__
 
+#include <stdint.h>
+
 enum {
 	TSHUT_POL_HIGH = 1 << 8,
 	TSHUT_POL_LOW = 0 << 8

src/southbridge/amd/sr5650/chip.h

@@ -17,6 +17,8 @@
 #ifndef SR5650_CHIP_H
 #define SR5650_CHIP_H
 
+#include <stdint.h>
+
 /* Member variables are defined in Config.lb. */
 struct southbridge_amd_sr5650_config
 {