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sc7280: Improve performance by removing delays in cpucp init 

As cpucp prepare takes 300 msec moving to before ramstage

BUG=b:218406702
TEST=Validated on qualcomm sc7280 development board observed
total timestamp as 1.73 sec from 1.97 sec

Change-Id: I1a727514810a505cd1005ae7f52e5215e404b3bb
Signed-off-by: Sudheer Kumar Amrabadi <quic_samrabad@quicinc.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63085
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
This commit is contained in:
Sudheer Kumar Amrabadi 2022-03-22 20:00:29 +05:30 committed by Julius Werner
parent 363202b435
commit dfe817e451
3 changed files with 7 additions and 5 deletions
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2
src/mainboard/google/herobrine/romstage.c
View File

@ -5,6 +5,7 @@
#include <soc/qclib_common.h> #include <soc/qclib_common.h>
#include "board.h" #include "board.h"
#include <soc/shrm.h> #include <soc/shrm.h>
#include <soc/cpucp.h>
static void prepare_usb(void) static void prepare_usb(void)
{ {
@ -18,6 +19,7 @@ static void prepare_usb(void)
void platform_romstage_main(void) void platform_romstage_main(void)
{ {
shrm_fw_load_reset(); shrm_fw_load_reset();
cpucp_prepare();
/* QCLib: DDR init & train */ /* QCLib: DDR init & train */
qclib_load_and_run(); qclib_load_and_run();
prepare_usb(); prepare_usb();

1
src/soc/qualcomm/sc7280/Makefile.inc
View File

@ -27,6 +27,7 @@ verstage-$(CONFIG_DRIVERS_UART) += ../common/qupv3_uart.c
################################################################################ ################################################################################
romstage-y += cbmem.c romstage-y += cbmem.c
romstage-y += shrm_load_reset.c romstage-y += shrm_load_reset.c
romstage-y += cpucp_load_reset.c
romstage-y += ../common/qclib.c romstage-y += ../common/qclib.c
romstage-y += ../common/mmu.c romstage-y += ../common/mmu.c
romstage-y += mmu.c romstage-y += mmu.c

9
src/soc/qualcomm/sc7280/cpucp_load_reset.c
View File

@ -11,13 +11,11 @@
void cpucp_prepare(void) void cpucp_prepare(void)
{ {
/* allow NS access to EPSS memory*/ /* allow NS access to EPSS memory */
setbits32(&epss_top->access_override, 0x1); setbits32(&epss_top->access_override, 0x1);
/* Enable subsystem clock. Required for CPUCP PDMEM access*/ /* Enable subsystem clock. Required for CPUCP PDMEM access */
setbits32(&epss_fast->epss_muc_clk_ctrl, 0x1); setbits32(&epss_fast->epss_muc_clk_ctrl, 0x1);
if (!wait_ms(300, ((read32(&epss_fast->epss_muc_clk_ctrl) & 0x1) != 0x1)))
printk(BIOS_ERR, "%s: cannot get CPUCP PDMEM access.\n", __func__);
} }
void cpucp_fw_load_reset(void) void cpucp_fw_load_reset(void)
@ -25,7 +23,8 @@ void cpucp_fw_load_reset(void)
struct prog cpucp_fw_prog = struct prog cpucp_fw_prog =
PROG_INIT(PROG_PAYLOAD, CONFIG_CBFS_PREFIX "/cpucp"); PROG_INIT(PROG_PAYLOAD, CONFIG_CBFS_PREFIX "/cpucp");
cpucp_prepare(); if (!wait_ms(300, (read32(&epss_fast->epss_muc_clk_ctrl) & 0x1) == 0x1))
printk(BIOS_ERR, "%s: cannot get CPUCP PDMEM access.\n", __func__);
if (!selfload(&cpucp_fw_prog)) if (!selfload(&cpucp_fw_prog))
die("SOC image: CPUCP load failed"); die("SOC image: CPUCP load failed");