sc7280: Improve performance by removing delays in cpucp init
As cpucp prepare takes 300 msec moving to before ramstage BUG=b:218406702 TEST=Validated on qualcomm sc7280 development board observed total timestamp as 1.73 sec from 1.97 sec Change-Id: I1a727514810a505cd1005ae7f52e5215e404b3bb Signed-off-by: Sudheer Kumar Amrabadi <quic_samrabad@quicinc.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63085 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
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@ -5,6 +5,7 @@
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#include <soc/qclib_common.h>
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#include "board.h"
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#include <soc/shrm.h>
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#include <soc/cpucp.h>
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static void prepare_usb(void)
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{
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@ -18,6 +19,7 @@ static void prepare_usb(void)
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void platform_romstage_main(void)
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{
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shrm_fw_load_reset();
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cpucp_prepare();
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/* QCLib: DDR init & train */
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qclib_load_and_run();
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prepare_usb();
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@ -27,6 +27,7 @@ verstage-$(CONFIG_DRIVERS_UART) += ../common/qupv3_uart.c
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################################################################################
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romstage-y += cbmem.c
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romstage-y += shrm_load_reset.c
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romstage-y += cpucp_load_reset.c
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romstage-y += ../common/qclib.c
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romstage-y += ../common/mmu.c
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romstage-y += mmu.c
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@ -11,13 +11,11 @@
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void cpucp_prepare(void)
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{
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/* allow NS access to EPSS memory*/
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/* allow NS access to EPSS memory */
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setbits32(&epss_top->access_override, 0x1);
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/* Enable subsystem clock. Required for CPUCP PDMEM access*/
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/* Enable subsystem clock. Required for CPUCP PDMEM access */
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setbits32(&epss_fast->epss_muc_clk_ctrl, 0x1);
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if (!wait_ms(300, ((read32(&epss_fast->epss_muc_clk_ctrl) & 0x1) != 0x1)))
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printk(BIOS_ERR, "%s: cannot get CPUCP PDMEM access.\n", __func__);
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}
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void cpucp_fw_load_reset(void)
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@ -25,7 +23,8 @@ void cpucp_fw_load_reset(void)
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struct prog cpucp_fw_prog =
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PROG_INIT(PROG_PAYLOAD, CONFIG_CBFS_PREFIX "/cpucp");
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cpucp_prepare();
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if (!wait_ms(300, (read32(&epss_fast->epss_muc_clk_ctrl) & 0x1) == 0x1))
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printk(BIOS_ERR, "%s: cannot get CPUCP PDMEM access.\n", __func__);
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if (!selfload(&cpucp_fw_prog))
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die("SOC image: CPUCP load failed");
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