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ec/google/chromeec: Fix dev ops for chromeec 

CB:38541 ("ec/google/chromeec: Add SSDT generator for ChromeOS EC")
added a new device_operations structure for chromeec for handling ACPI
SSDT generation. However, this resulted in the original
device_operations which handled lpc read resources to be skipped. This
change fixes the above regression by combining the device operations
for reading resources and ACPI SSDT generation into a single structure
and retains the old logic for enabling of pnp devices.

Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I3a242f4b15603f957e0e81d121e5766fccf3c28d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39321
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Furquan Shaikh 2020-03-05 08:06:27 -08:00 committed by Patrick Georgi
parent 04b02069e2
commit e0060a80f0
5 changed files with 12 additions and 33 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/ec/google/chromeec/Makefile.inc
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@ -28,7 +28,7 @@ verstage-y += ec.c crosec_proto.c vstore.c
verstage-$(CONFIG_EC_GOOGLE_CHROMEEC_I2C) += ec_i2c.c
verstage-$(CONFIG_EC_GOOGLE_CHROMEEC_LPC) += ec_lpc.c
verstage-$(CONFIG_EC_GOOGLE_CHROMEEC_SPI) += ec_spi.c
ramstage-$(CONFIG_HAVE_ACPI_TABLES) += ec_chip.c
ramstage-$(CONFIG_HAVE_ACPI_TABLES) += ec_acpi.c
ramstage-$(CONFIG_VBOOT) += vboot_storage.c
smm-$(CONFIG_VBOOT) += vboot_storage.c

25
src/ec/google/chromeec/ec.c
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@ -1525,28 +1525,3 @@ int google_chromeec_wait_for_displayport(long timeout)
return 1;
}
#if CONFIG(HAVE_ACPI_TABLES) && !DEVTREE_EARLY
static struct device_operations ec_chromeec_ops = {
.acpi_name = google_chromeec_acpi_name,
.acpi_fill_ssdt_generator = google_chromeec_fill_ssdt_generator,
};
#endif
/* ec_lpc, ec_spi, or ec_i2c can override this */
__weak void google_ec_enable_extra(struct device *dev)
{
}
static void google_chromeec_enable(struct device *dev)
{
#if CONFIG(HAVE_ACPI_TABLES) && !DEVTREE_EARLY
dev->ops = &ec_chromeec_ops;
#endif
google_ec_enable_extra(dev);
}
struct chip_operations ec_google_chromeec_ops = {
CHIP_NAME("Google Chrome EC")
.enable_dev = google_chromeec_enable
};

5
src/ec/google/chromeec/ec.h
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@ -350,9 +350,4 @@ const char *google_chromeec_acpi_name(const struct device *dev);
#endif /* HAVE_ACPI_TABLES */
/*
* Allows bus-specific EC code to perform actions when the device is enabled.
*/
void google_ec_enable_extra(struct device *dev);
#endif /* _EC_GOOGLE_CHROMEEC_EC_H */

0
src/ec/google/chromeec/ec_chip.c → src/ec/google/chromeec/ec_acpi.c
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13
src/ec/google/chromeec/ec_lpc.c
View File

@ -451,18 +451,27 @@ static struct device_operations ops = {
.init = lpc_ec_init,
.read_resources = lpc_ec_read_resources,
.enable_resources = DEVICE_NOOP,
.set_resources = DEVICE_NOOP
.set_resources = DEVICE_NOOP,
#if CONFIG(HAVE_ACPI_TABLES)
.acpi_name = google_chromeec_acpi_name,
.acpi_fill_ssdt_generator = google_chromeec_fill_ssdt_generator,
#endif
};
static struct pnp_info pnp_dev_info[] = {
{ NULL, 0, 0, 0, }
};
void google_ec_enable_extra(struct device *dev)
static void enable_dev(struct device *dev)
{
pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
}
struct chip_operations ec_google_chromeec_ops = {
CHIP_NAME("Google Chrome EC")
.enable_dev = enable_dev,
};
static int google_chromeec_data_ready(u16 port)
{
return google_chromeec_status_check(port, EC_LPC_CMDR_DATA,