soc/intel/cannonlake: Add DisableHeciRetry to config

Add DisableHeciRetry to the chip config and parse it in romstage.

Change-Id: I460b51834c7de42e68fe3d54c66acd1022a3bdaf
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40756
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>

src/soc/intel/cannonlake/chip.h

@@ -194,6 +194,7 @@ struct soc_intel_cannonlake_config {
 
 	/* Heci related */
 	uint8_t Heci3Enabled;
+	uint8_t DisableHeciRetry;
 
 	/* Gfx related */
 	uint8_t IgdDvmt50PreAlloc;

src/soc/intel/cannonlake/romstage/fsp_params.c

@@ -128,6 +128,10 @@ static void soc_memory_init_params(FSPM_UPD *mupd, const config_t *config)
 				config->sata_port[i].TxGen3DeEmph;
 		}
 	}
+#if !CONFIG(SOC_INTEL_COMETLAKE)
+	if (config->DisableHeciRetry)
+		tconfig->DisableHeciRetry = config->DisableHeciRetry;
+#endif
 }
 
 void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)