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soc/intel/cannonlake: Add DisableHeciRetry to config 

Add DisableHeciRetry to the chip config and parse it in romstage.

Change-Id: I460b51834c7de42e68fe3d54c66acd1022a3bdaf
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40756
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
This commit is contained in:
Christian Walter 2020-04-27 18:11:51 +02:00 committed by Patrick Rudolph
parent 066007590f
commit e01054d86e
2 changed files with 5 additions and 0 deletions
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1
src/soc/intel/cannonlake/chip.h
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@ -194,6 +194,7 @@ struct soc_intel_cannonlake_config {
/* Heci related */ /* Heci related */
uint8_t Heci3Enabled; uint8_t Heci3Enabled;
uint8_t DisableHeciRetry;
/* Gfx related */ /* Gfx related */
uint8_t IgdDvmt50PreAlloc; uint8_t IgdDvmt50PreAlloc;

4
src/soc/intel/cannonlake/romstage/fsp_params.c
View File

@ -128,6 +128,10 @@ static void soc_memory_init_params(FSPM_UPD *mupd, const config_t *config)
config->sata_port[i].TxGen3DeEmph; config->sata_port[i].TxGen3DeEmph;
} }
} }
#if !CONFIG(SOC_INTEL_COMETLAKE)
if (config->DisableHeciRetry)
tconfig->DisableHeciRetry = config->DisableHeciRetry;
#endif
} }
void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)