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mb/google(sandybrige): Clean up LPC and IOAPIC configuration 

Only set LPC decode bits that the generic PCH code doesn't set yet. And
don't enable the IOAPIC, which is already done by generic code.

Change-Id: I9d2f6a9ad3f5d83573e07596f2763edc75f4ee64
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36891
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Nico Huber 2019-11-17 01:24:44 +01:00 committed by Patrick Georgi
parent 3ad93615be
commit e036aaede4
4 changed files with 2 additions and 43 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
src/mainboard/google/butterfly/early_init.c
View File

@ -28,13 +28,6 @@
#include <vendorcode/google/chromeos/chromeos.h>
#endif
void mainboard_pch_lpc_setup(void)
{
/* EC Decode Range Port60/64 and Port62/66 */
/* Enable EC and PS/2 Keyboard/Mouse*/
pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN | MC_LPC_EN);
}
void mainboard_late_rcba_config(void)
{
u32 reg32;
@ -76,11 +69,6 @@ void mainboard_late_rcba_config(void)
DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD);
DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD);
/* Enable IOAPIC (generic) */
RCBA16(OIC) = 0x0100;
/* PCH BWG says to read back the IOAPIC enable register */
(void) RCBA16(OIC);
/* Disable unused devices (board specific) */
reg32 = RCBA32(FD);
/* Disable PCI bridge so MRC does not probe this bus */

10
src/mainboard/google/link/early_init.c
View File

@ -34,9 +34,8 @@
void mainboard_pch_lpc_setup(void)
{
/* Enable PS/2 Keyboard/Mouse, EC areas and COM1 */
pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN | MC_LPC_EN | \
GAMEL_LPC_EN | COMA_LPC_EN);
/* Enable additional 0x200..0x207 for EC */
pci_or_config16(PCH_LPC_DEV, LPC_EN, GAMEL_LPC_EN);
}
void mainboard_late_rcba_config(void)
@ -74,11 +73,6 @@ void mainboard_late_rcba_config(void)
DIR_ROUTE(D26IR, PIRQF, PIRQE, PIRQG, PIRQH);
DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD);
DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD);
/* Enable IOAPIC (generic) */
RCBA16(OIC) = 0x0100;
/* PCH BWG says to read back the IOAPIC enable register */
(void) RCBA16(OIC);
}
static uint8_t *locate_spd(void)

5
src/mainboard/google/parrot/early_init.c
View File

@ -68,11 +68,6 @@ void mainboard_late_rcba_config(void)
DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD);
DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD);
/* Enable IOAPIC (generic) */
RCBA16(OIC) = 0x0100;
/* PCH BWG says to read back the IOAPIC enable register */
(void) RCBA16(OIC);
/* Disable unused devices (board specific) */
reg32 = RCBA32(FD);
/* Disable PCI bridge so MRC does not probe this bus */

18
src/mainboard/google/stout/early_init.c
View File

@ -30,19 +30,6 @@
#include "ec.h"
#include "onboard.h"
void mainboard_pch_lpc_setup(void)
{
/*
* Enable:
* EC Decode Range Port62/66
* SuperIO Port2E/2F
* PS/2 Keyboard/Mouse Port60/64
* FDD Port3F0h-3F5h and Port3F7h
*/
pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN | MC_LPC_EN |
CNF1_LPC_EN | FDD_LPC_EN);
}
void mainboard_late_rcba_config(void)
{
u32 reg32;
@ -85,11 +72,6 @@ void mainboard_late_rcba_config(void)
DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD);
DIR_ROUTE(D20IR, PIRQD, PIRQE, PIRQF, PIRQG);
/* Enable IOAPIC (generic) */
RCBA16(OIC) = 0x0100;
/* PCH BWG says to read back the IOAPIC enable register */
(void) RCBA16(OIC);
/* Disable unused devices (board specific) */
reg32 = RCBA32(FD);
/* Disable PCI bridge so MRC does not probe this bus */