e036aaede4
Only set LPC decode bits that the generic PCH code doesn't set yet. And don't enable the IOAPIC, which is already done by generic code. Change-Id: I9d2f6a9ad3f5d83573e07596f2763edc75f4ee64 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36891 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
156 lines
5.1 KiB
C
156 lines
5.1 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007-2010 coresystems GmbH
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* Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <stdint.h>
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#include <device/pci_ops.h>
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#include <device/pci_def.h>
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#include <cpu/x86/lapic.h>
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#include <arch/acpi.h>
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#include <northbridge/intel/sandybridge/sandybridge.h>
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#include <northbridge/intel/sandybridge/raminit.h>
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#include <northbridge/intel/sandybridge/raminit_native.h>
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#include <southbridge/intel/bd82x6x/pch.h>
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#include <southbridge/intel/common/gpio.h>
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#include "ec/compal/ene932/ec.h"
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void mainboard_late_rcba_config(void)
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{
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u32 reg32;
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/*
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* GFX INTA -> PIRQA (MSI)
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* D28IP_P2IP WLAN INTA -> PIRQB
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* D28IP_P3IP ETH0 INTC -> PIRQD
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* D29IP_E1P EHCI1 INTA -> PIRQE
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* D26IP_E2P EHCI2 INTA -> PIRQE
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* D31IP_SIP SATA INTA -> PIRQF (MSI)
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* D31IP_SMIP SMBUS INTB -> PIRQG
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* D31IP_TTIP THRT INTC -> PIRQH
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* D27IP_ZIP HDA INTA -> PIRQG (MSI)
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*
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* Trackpad DVT PIRQA (16)
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* Trackpad DVT PIRQE (20)
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*/
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/* Device interrupt pin register (board specific) */
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RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) |
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(INTB << D31IP_SMIP) | (INTA << D31IP_SIP);
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RCBA32(D30IP) = (NOINT << D30IP_PIP);
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RCBA32(D29IP) = (INTA << D29IP_E1P);
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RCBA32(D28IP) = (NOINT << D28IP_P1IP) | (INTA << D28IP_P2IP) |
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(INTC << D28IP_P3IP) | (NOINT << D28IP_P4IP) |
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(NOINT << D28IP_P5IP) | (NOINT << D28IP_P6IP) |
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(NOINT << D28IP_P7IP) | (NOINT << D28IP_P8IP);
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RCBA32(D27IP) = (INTA << D27IP_ZIP);
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RCBA32(D26IP) = (INTA << D26IP_E2P);
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RCBA32(D25IP) = (NOINT << D25IP_LIP);
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RCBA32(D22IP) = (NOINT << D22IP_MEI1IP);
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/* Device interrupt route registers */
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DIR_ROUTE(D31IR, PIRQB, PIRQH, PIRQA, PIRQC);
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DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG);
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DIR_ROUTE(D28IR, PIRQB, PIRQC, PIRQD, PIRQE);
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DIR_ROUTE(D27IR, PIRQA, PIRQH, PIRQA, PIRQB);
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DIR_ROUTE(D26IR, PIRQF, PIRQE, PIRQG, PIRQH);
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DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD);
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DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD);
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/* Disable unused devices (board specific) */
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reg32 = RCBA32(FD);
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/* Disable PCI bridge so MRC does not probe this bus */
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reg32 |= PCH_DISABLE_P2P;
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RCBA32(FD) = reg32;
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}
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void mainboard_fill_pei_data(struct pei_data *pei_data)
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{
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struct pei_data pei_data_template = {
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.pei_version = PEI_VERSION,
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.mchbar = (uintptr_t)DEFAULT_MCHBAR,
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.dmibar = (uintptr_t)DEFAULT_DMIBAR,
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.epbar = DEFAULT_EPBAR,
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.pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
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.smbusbar = SMBUS_IO_BASE,
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.wdbbar = 0x4000000,
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.wdbsize = 0x1000,
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.hpet_address = CONFIG_HPET_ADDRESS,
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.rcba = (uintptr_t)DEFAULT_RCBABASE,
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.pmbase = DEFAULT_PMBASE,
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.gpiobase = DEFAULT_GPIOBASE,
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.thermalbase = 0xfed08000,
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.system_type = 0, // 0 Mobile, 1 Desktop/Server
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.tseg_size = CONFIG_SMM_TSEG_SIZE,
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.spd_addresses = { 0xA0, 0x00,0xA4,0x00 },
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.ts_addresses = { 0x00, 0x00, 0x00, 0x00 },
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.ec_present = 1,
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// 0 = leave channel enabled
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// 1 = disable dimm 0 on channel
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// 2 = disable dimm 1 on channel
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// 3 = disable dimm 0+1 on channel
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.dimm_channel0_disabled = 2,
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.dimm_channel1_disabled = 2,
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.max_ddr3_freq = 1600,
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.usb_port_config = {
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/* Empty and onboard Ports 0-7, set to un-used pin OC3 */
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{ 0, 3, 0x0000 }, /* P0: Empty */
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{ 1, 0, 0x0040 }, /* P1: Left USB 1 (OC0) */
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{ 1, 1, 0x0040 }, /* P2: Left USB 2 (OC1) */
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{ 1, 1, 0x0040 }, /* P3: Left USB 3 (OC1) */
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{ 0, 3, 0x0000 }, /* P4: Empty */
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{ 0, 3, 0x0000 }, /* P5: Empty */
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{ 0, 3, 0x0000 }, /* P6: Empty */
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{ 0, 3, 0x0000 }, /* P7: Empty */
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/* Empty and onboard Ports 8-13, set to un-used pin OC4 */
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{ 1, 4, 0x0040 }, /* P8: MiniPCIe (WLAN) (no OC) */
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{ 0, 4, 0x0000 }, /* P9: Empty */
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{ 1, 4, 0x0040 }, /* P10: Camera (no OC) */
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{ 0, 4, 0x0000 }, /* P11: Empty */
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{ 0, 4, 0x0000 }, /* P12: Empty */
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{ 0, 4, 0x0000 }, /* P13: Empty */
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},
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};
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*pei_data = pei_data_template;
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}
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const struct southbridge_usb_port mainboard_usb_ports[] = {
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/* enabled power usb oc pin */
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{ 0, 0, -1 }, /* P0: Empty */
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{ 1, 0, 0 }, /* P1: Left USB 1 (OC0) */
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{ 1, 0, 1 }, /* P2: Left USB 2 (OC1) */
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{ 1, 0, 1 }, /* P3: Left USB 3 (OC1) */
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{ 0, 0, -1 }, /* P4: Empty */
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{ 0, 0, -1 }, /* P5: Empty */
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{ 0, 0, -1 }, /* P6: Empty */
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{ 0, 0, -1 }, /* P7: Empty */
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/* Empty and onboard Ports 8-13, set to un-used pin OC4 */
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{ 1, 0, -1 }, /* P8: MiniPCIe (WLAN) (no OC) */
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{ 0, 0, -1 }, /* P9: Empty */
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{ 1, 0, -1 }, /* P10: Camera (no OC) */
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{ 0, 0, -1 }, /* P11: Empty */
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{ 0, 0, -1 }, /* P12: Empty */
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{ 0, 0, -1 }, /* P13: Empty */
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};
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void mainboard_get_spd(spd_raw_data *spd, bool id_only)
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{
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read_spd(&spd[0], 0x50, id_only);
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read_spd(&spd[2], 0x52, id_only);
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}
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int mainboard_should_reset_usb(int s3resume)
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{
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return !s3resume;
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}
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