AMD/spi: Do not reset fifo after skipping the sent bytes
After we skip the bytes we send, the fifo pointer is at right position. Reseting the fifo will change it to a wrong place. Please view the flashrom code, which tells the same thing. https://code.coreboot.org/p/flashrom/source/tree/HEAD/trunk/sb600spi.c#L257 Change-Id: I31d487ce32c0d7ca3dead36d2b14611e73b1ad60 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/14955 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
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@ -143,7 +143,6 @@ int spi_xfer(struct spi_slave *slave, const void *dout,
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cmd = spi_read(SPI_REG_FIFO);
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cmd = spi_read(SPI_REG_FIFO);
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}
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}
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reset_internal_fifo_pointer();
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for (count = 0; count < bytesin; count++, din++) {
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for (count = 0; count < bytesin; count++, din++) {
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*(uint8_t *)din = spi_read(SPI_REG_FIFO);
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*(uint8_t *)din = spi_read(SPI_REG_FIFO);
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}
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}
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