include/cpu/amd/msr: rename MSR_PSP_ADDR to PSP_ADDR_MSR
The new name is more consistent with the rest of the MSR definitions. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5666d9837c61881639b5f292553a728e49c5ceb2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50855 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -78,7 +78,7 @@
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#define LS_CFG2_MSR 0xC001102D
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#define IBS_OP_DATA3_MSR 0xC0011037
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#define S3_RESUME_EIP_MSR 0xC00110E0
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#define MSR_PSP_ADDR 0xc00110a2
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#define PSP_ADDR_MSR 0xc00110a2
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#define MSR_PATCH_LEVEL 0x0000008B
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#define CORE_PERF_BOOST_CTRL 0x15c
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@ -13,9 +13,9 @@
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static uintptr_t soc_get_psp_base_address(void)
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{
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uintptr_t psp_mmio = rdmsr(MSR_PSP_ADDR).lo;
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uintptr_t psp_mmio = rdmsr(PSP_ADDR_MSR).lo;
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if (!psp_mmio)
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printk(BIOS_ERR, "PSP: MSR_PSP_ADDR uninitialized\n");
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printk(BIOS_ERR, "PSP: PSP_ADDR_MSR uninitialized\n");
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return psp_mmio;
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}
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@ -76,10 +76,10 @@ static void model_15_init(struct device *dev)
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uint32_t psp_bar; /* Note: NDA BKDG names this 32-bit register BAR3 */
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psp_bar = pci_read_config32(SOC_PSP_DEV, PCI_BASE_ADDRESS_4);
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psp_bar &= ~PCI_BASE_ADDRESS_MEM_ATTR_MASK;
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psp_msr = rdmsr(MSR_PSP_ADDR);
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psp_msr = rdmsr(PSP_ADDR_MSR);
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if (psp_msr.lo == 0) {
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psp_msr.lo = psp_bar;
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wrmsr(MSR_PSP_ADDR, psp_msr);
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wrmsr(PSP_ADDR_MSR, psp_msr);
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}
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}
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@ -45,9 +45,9 @@ void *soc_get_mbox_address(void)
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/* Determine if Bar3Hide has been set, and if hidden get the base from
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* the MSR instead. */
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if (pci_read_config32(SOC_PSP_DEV, PSP_BAR_ENABLES) & BAR3HIDE) {
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psp_mmio = rdmsr(MSR_PSP_ADDR).lo;
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psp_mmio = rdmsr(PSP_ADDR_MSR).lo;
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if (!psp_mmio) {
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printk(BIOS_WARNING, "PSP: BAR hidden, MSR_PSP_ADDR uninitialized\n");
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printk(BIOS_WARNING, "PSP: BAR hidden, PSP_ADDR_MSR uninitialized\n");
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return 0;
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}
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} else {
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