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include/cpu/amd/msr: rename MSR_PSP_ADDR to PSP_ADDR_MSR 

The new name is more consistent with the rest of the MSR definitions.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5666d9837c61881639b5f292553a728e49c5ceb2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50855
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Felix Held 2021-02-17 22:22:21 +01:00
parent 285dd6ec3a
commit e09294f57a
4 changed files with 7 additions and 7 deletions
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2
src/include/cpu/amd/msr.h
View File

@ -78,7 +78,7 @@
#define LS_CFG2_MSR 0xC001102D #define LS_CFG2_MSR 0xC001102D
#define IBS_OP_DATA3_MSR 0xC0011037 #define IBS_OP_DATA3_MSR 0xC0011037
#define S3_RESUME_EIP_MSR 0xC00110E0 #define S3_RESUME_EIP_MSR 0xC00110E0
#define MSR_PSP_ADDR 0xc00110a2 #define PSP_ADDR_MSR 0xc00110a2
#define MSR_PATCH_LEVEL 0x0000008B #define MSR_PATCH_LEVEL 0x0000008B
#define CORE_PERF_BOOST_CTRL 0x15c #define CORE_PERF_BOOST_CTRL 0x15c

4
src/soc/amd/common/block/psp/psp_gen2.c
View File

@ -13,9 +13,9 @@
static uintptr_t soc_get_psp_base_address(void) static uintptr_t soc_get_psp_base_address(void)
{ {
uintptr_t psp_mmio = rdmsr(MSR_PSP_ADDR).lo; uintptr_t psp_mmio = rdmsr(PSP_ADDR_MSR).lo;
if (!psp_mmio) if (!psp_mmio)
printk(BIOS_ERR, "PSP: MSR_PSP_ADDR uninitialized\n"); printk(BIOS_ERR, "PSP: PSP_ADDR_MSR uninitialized\n");
return psp_mmio; return psp_mmio;
} }

4
src/soc/amd/stoneyridge/cpu.c
View File

@ -76,10 +76,10 @@ static void model_15_init(struct device *dev)
uint32_t psp_bar; /* Note: NDA BKDG names this 32-bit register BAR3 */ uint32_t psp_bar; /* Note: NDA BKDG names this 32-bit register BAR3 */
psp_bar = pci_read_config32(SOC_PSP_DEV, PCI_BASE_ADDRESS_4); psp_bar = pci_read_config32(SOC_PSP_DEV, PCI_BASE_ADDRESS_4);
psp_bar &= ~PCI_BASE_ADDRESS_MEM_ATTR_MASK; psp_bar &= ~PCI_BASE_ADDRESS_MEM_ATTR_MASK;
psp_msr = rdmsr(MSR_PSP_ADDR); psp_msr = rdmsr(PSP_ADDR_MSR);
if (psp_msr.lo == 0) { if (psp_msr.lo == 0) {
psp_msr.lo = psp_bar; psp_msr.lo = psp_bar;
wrmsr(MSR_PSP_ADDR, psp_msr); wrmsr(PSP_ADDR_MSR, psp_msr);
} }
} }

4
src/soc/amd/stoneyridge/psp.c
View File

@ -45,9 +45,9 @@ void *soc_get_mbox_address(void)
/* Determine if Bar3Hide has been set, and if hidden get the base from /* Determine if Bar3Hide has been set, and if hidden get the base from
* the MSR instead. */ * the MSR instead. */
if (pci_read_config32(SOC_PSP_DEV, PSP_BAR_ENABLES) & BAR3HIDE) { if (pci_read_config32(SOC_PSP_DEV, PSP_BAR_ENABLES) & BAR3HIDE) {
psp_mmio = rdmsr(MSR_PSP_ADDR).lo; psp_mmio = rdmsr(PSP_ADDR_MSR).lo;
if (!psp_mmio) { if (!psp_mmio) {
printk(BIOS_WARNING, "PSP: BAR hidden, MSR_PSP_ADDR uninitialized\n"); printk(BIOS_WARNING, "PSP: BAR hidden, PSP_ADDR_MSR uninitialized\n");
return 0; return 0;
} }
} else { } else {