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soc/amd/picasso: Update for USB3.1 

Change to the appropriate device IDs.  Remove the ehci resource
call.  Remove overcurrent settings, as this will be passed to
AGESA in later change.

Remove unused USB2 ACPI name assignment.

Change-Id: Ic287a05b30ca03e3371cc4a30aaa93b236c6d3fb
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34420
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Marshall Dawson 2019-07-09 18:12:03 -05:00 committed by Martin Roth
parent 6261141579
commit e0fd9a60e7
4 changed files with 8 additions and 70 deletions
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16
src/soc/amd/picasso/acpi/sb_pci0_fch.asl
View File

@ -243,20 +243,6 @@ Field( SMIC, ByteAcc, NoLock, Preserve) {
offset (0x1e5f), /* SATA D3 State */
SADS, 3,
offset (0x1e64), /* USB2 D3 Control */
U2TD, 2,
, 1,
U2PD, 1,
offset (0x1e65), /* USB2 D3 State */
U2DS, 3,
offset (0x1e6e), /* USB3 D3 Control */
U3TD, 2,
, 1,
U3PD, 1,
offset (0x1e6f), /* USB3 D3 State */
U3DS, 3,
offset (0x1e71), /* SD D3 State */
SDDS, 3,
@ -456,7 +442,6 @@ Method(FDDC, 2, Serialized)
if(LEqual(I3TD, 3)) {
if(LEqual(U0TD, 3)) {
if(LEqual(U1TD, 3)) {
if(LEqual(U2TD, 3)) {
Store(Zero, PG2_)
}
}
@ -464,7 +449,6 @@ Method(FDDC, 2, Serialized)
}
}
}
}
Release(FDAS)
}

13
src/soc/amd/picasso/chip.c
View File

@ -49,19 +49,6 @@ const char *soc_acpi_name(const struct device *dev)
case 0:
/* Root Hub */
return "RHUB";
case 2:
/* USB2 ports */
switch (dev->path.usb.port_id) {
case 0: return "HS01";
case 1: return "HS02";
case 2: return "HS03";
case 3: return "HS04";
case 4: return "HS05";
case 5: return "HS06";
case 6: return "HS07";
case 7: return "HS08";
}
break;
case 3:
/* USB3 ports */
switch (dev->path.usb.port_id) {

9
src/soc/amd/picasso/include/soc/southbridge.h
View File

@ -357,15 +357,6 @@ uint32_t get_uma_size(void);
* @return 64bit base address
*/
uint64_t get_uma_base(void);
/*
* Call the mainboard to get the USB Over Current Map. The mainboard
* returns the map and 0 on Success or -1 on error or no map. There is
* a default weak function in usb.c if the mainboard doesn't have any
* over current support.
*/
#define USB_OC_DISABLE_ALL 0xffff
int mainboard_get_xhci0_oc_map(uint16_t *usb_oc_map);
int mainboard_get_xhci1_oc_map(uint16_t *usb_oc_map);
/* Initialize all the i2c buses that are marked with early init. */
void i2c_soc_early_init(void);

38
src/soc/amd/picasso/usb.c
View File

@ -24,31 +24,11 @@
#include <soc/southbridge.h>
#include <amdblocks/acpimmio.h>
static void set_usb_over_current(struct device *dev)
static void picasso_usb_init(struct device *dev)
{
uint16_t map = USB_OC_DISABLE_ALL;
/* USB overcurrent configuration is programmed inside the FSP */
if (dev->path.pci.devfn == XHCI0_DEVFN) {
if (mainboard_get_xhci0_oc_map(&map) == 0)
; // TODO
}
if (dev->path.pci.devfn == XHCI1_DEVFN) {
if (mainboard_get_xhci1_oc_map(&map) == 0)
; // TODO
}
}
int __weak mainboard_get_xhci0_oc_map(uint16_t *map)
{
printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
return -1;
}
int __weak mainboard_get_xhci1_oc_map(uint16_t *map)
{
printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
return -1;
printk(BIOS_DEBUG, "%s\n", __func__);
}
static struct pci_operations lops_pci = {
@ -56,22 +36,18 @@ static struct pci_operations lops_pci = {
};
static struct device_operations usb_ops = {
.read_resources = pci_ehci_read_resources,
.read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = set_usb_over_current,
.init = picasso_usb_init,
.scan_bus = scan_static_bus,
.acpi_name = soc_acpi_name,
.ops_pci = &lops_pci,
};
static const unsigned short pci_device_ids[] = {
PCI_DEVICE_ID_AMD_SB900_USB_18_0,
PCI_DEVICE_ID_AMD_SB900_USB_18_2,
PCI_DEVICE_ID_AMD_SB900_USB_20_5,
PCI_DEVICE_ID_AMD_CZ_USB_0,
PCI_DEVICE_ID_AMD_CZ_USB_1,
PCI_DEVICE_ID_AMD_CZ_USB3_0,
PCI_DEVICE_ID_AMD_PCO_XHCI0,
PCI_DEVICE_ID_AMD_PCO_XHCI1,
0
};