mb/asrock/h110m: Relocate devicetree settings
Some settings are suspicious, and have been annotated with FIXMEs. Tested with BUILD_TIMELESS=1, its coreboot.rom does not change. Change-Id: I7755867cb92745f542a4261db5dd118ca905612b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43919 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Angel Pons
Patrick Georgi
parent
9addda3c41
commit
e18cdf4d93
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@ -18,9 +18,6 @@ chip soc/intel/skylake
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register "gpe0_dw1" = "GPP_D"
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register "gpe0_dw1" = "GPP_D"
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register "gpe0_dw2" = "GPP_E"
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register "gpe0_dw2" = "GPP_E"
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# Set @0x280-0x2ff I/O Range for SuperIO HWM
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register "gen1_dec" = "0x007c0281"
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# Enable "Intel Speed Shift Technology"
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# Enable "Intel Speed Shift Technology"
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register "speed_shift_enable" = "1"
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register "speed_shift_enable" = "1"
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@ -28,19 +25,9 @@ chip soc/intel/skylake
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register "dptf_enable" = "1"
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register "dptf_enable" = "1"
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# FSP Configuration
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# FSP Configuration
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register "ScsEmmcHs400Enabled" = "0"
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register "ScsSdCardEnabled" = "0"
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register "HeciEnabled" = "0"
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register "SkipExtGfxScan" = "0"
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register "PrimaryDisplay" = "Display_PEG"
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register "PrimaryDisplay" = "Display_PEG"
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register "Device4Enable" = "1"
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register "SaGv" = "SaGv_Enabled"
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register "SaGv" = "SaGv_Enabled"
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register "PmTimerDisabled" = "0"
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register "PmTimerDisabled" = "0"
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register "DspEnable" = "0"
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register "PchHdaVcType" = "Vc1"
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# Set LPC Serial IRQ mode
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register "serirq_mode" = "SERIRQ_CONTINUOUS"
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# Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch
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# Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch
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# SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s
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# SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s
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@ -122,50 +109,6 @@ chip soc/intel/skylake
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.voltage_limit = 1520 \
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.voltage_limit = 1520 \
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}"
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}"
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# USB
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register "usb2_ports[0]" = "USB2_PORT_MID(OC0)"
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register "usb2_ports[1]" = "USB2_PORT_MID(OC0)"
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register "usb2_ports[2]" = "USB2_PORT_MID(OC4)"
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register "usb2_ports[3]" = "USB2_PORT_MID(OC4)"
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register "usb2_ports[4]" = "USB2_PORT_MID(OC2)"
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register "usb2_ports[5]" = "USB2_PORT_MID(OC2)"
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register "usb2_ports[6]" = "USB2_PORT_MID(OC0)"
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register "usb2_ports[7]" = "USB2_PORT_MID(OC0)"
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register "usb2_ports[8]" = "USB2_PORT_MID(OC0)"
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register "usb2_ports[9]" = "USB2_PORT_MID(OC0)"
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register "usb2_ports[10]" = "USB2_PORT_MID(OC1)"
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register "usb2_ports[11]" = "USB2_PORT_MID(OC1)"
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register "usb2_ports[12]" = "USB2_PORT_MID(OC_SKIP)"
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register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)"
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register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)"
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register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)"
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register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC3)"
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register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)"
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register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC1)"
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register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC1)"
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register "usb3_ports[6]" = "USB3_PORT_DEFAULT(OC_SKIP)"
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register "usb3_ports[7]" = "USB3_PORT_DEFAULT(OC_SKIP)"
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register "usb3_ports[8]" = "USB3_PORT_DEFAULT(OC_SKIP)"
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register "usb3_ports[9]" = "USB3_PORT_DEFAULT(OC_SKIP)"
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# SATA
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register "SataSalpSupport" = "1"
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# SATA4 and SATA5 are located in the lower right corner of the board,
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# but they are not populated. This is because the same PCB is used to
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# make boards with better PCHs, which can have up to six SATA ports.
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# However, the H110 PCH only has four SATA ports, which explains why
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# two connectors are missing.
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register "SataPortsEnable" = "{ \
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[0] = 1, \
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[1] = 1, \
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[2] = 1, \
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[3] = 1, \
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[4] = 0, \
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[5] = 0, \
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[6] = 0, \
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[7] = 0, \
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}"
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# PCH UART, SPI, I2C
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# PCH UART, SPI, I2C
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register "SerialIoDevMode" = "{ \
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register "SerialIoDevMode" = "{ \
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[PchSerialIoIndexI2C0] = PchSerialIoDisabled, \
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[PchSerialIoIndexI2C0] = PchSerialIoDisabled, \
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@ -181,55 +124,6 @@ chip soc/intel/skylake
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[PchSerialIoIndexUart2] = PchSerialIoDisabled, \
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[PchSerialIoIndexUart2] = PchSerialIoDisabled, \
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}"
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}"
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# Set params for PEG 0:1:0
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register "Peg0MaxLinkWidth" = "Peg0_x16"
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# Configure PCIe clockgen in PCH
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# PEG0 uses SRCCLKREQ0 and CLKSRC0
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register "PcieRpClkReqSupport[0]" = "1"
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register "PcieRpClkReqNumber[0]" = "0"
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register "PcieRpClkSrcNumber[0]" = "0"
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# Enable Root port 6(x1) for LAN.
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register "PcieRpEnable[5]" = "1"
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# Disable CLKREQ#, since onboard LAN is always present
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register "PcieRpClkReqSupport[5]" = "0"
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# Enable Advanced Error Reporting
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register "PcieRpAdvancedErrorReporting[5]" = "1"
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# Enable Latency Tolerance Reporting Mechanism
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register "PcieRpLtrEnable[5]" = "1"
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# Use CLK SRC 1
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register "PcieRpClkSrcNumber[5]" = "1"
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# Enable Root port 5 (x1) for PCIE slot.
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register "PcieRpEnable[4]" = "1"
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# Enable CLKREQ#
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register "PcieRpClkReqSupport[4]" = "1"
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# Use SRCCLKREQ2#
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register "PcieRpClkReqNumber[4]" = "2"
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# Enable Advanced Error Reporting
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register "PcieRpAdvancedErrorReporting[4]" = "1"
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# Enable Latency Tolerance Reporting Mechanism
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register "PcieRpLtrEnable[4]" = "1"
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# Use CLK SRC 2
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register "PcieRpClkSrcNumber[4]" = "2"
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# Use Hot Plug subsystem
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register "PcieRpHotPlug[4]" = "1"
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# Enable Root port 7(x1) for PCIE slot.
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register "PcieRpEnable[6]" = "1"
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# Enable CLKREQ#
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register "PcieRpClkReqSupport[6]" = "1"
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# Use SRCCLKREQ3#
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register "PcieRpClkReqNumber[6]" = "3"
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# Enable Advanced Error Reporting
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register "PcieRpAdvancedErrorReporting[6]" = "1"
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# Enable Latency Tolerance Reporting Mechanism
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register "PcieRpLtrEnable[6]" = "1"
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# Use CLK SRC 3
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register "PcieRpClkSrcNumber[6]" = "3"
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# Use Hot Plug subsystem
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register "PcieRpHotPlug[6]" = "1"
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# PL2 override 91W
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# PL2 override 91W
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register "power_limits_config" = "{
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register "power_limits_config" = "{
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.tdp_pl2_override = 91,
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.tdp_pl2_override = 91,
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@ -247,14 +141,49 @@ chip soc/intel/skylake
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end
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end
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device pci 01.0 on # PEG
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device pci 01.0 on # PEG
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subsystemid 0x1849 0x1901
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subsystemid 0x1849 0x1901
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register "Peg0MaxLinkWidth" = "Peg0_x16"
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register "SkipExtGfxScan" = "0"
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# Configure PCIe clockgen in PCH
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register "PcieRpClkReqSupport[0]" = "1"
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register "PcieRpClkReqNumber[0]" = "0"
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register "PcieRpClkSrcNumber[0]" = "0"
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end
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end
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device pci 02.0 on # Integrated Graphics Device
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device pci 02.0 on # Integrated Graphics Device
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subsystemid 0x1849 0x1912
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subsystemid 0x1849 0x1912
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end
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end
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device pci 04.0 on end # Thermal Subsystem
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device pci 04.0 on # Thermal Subsystem
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register "Device4Enable" = "1"
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end
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device pci 08.0 off end # Gaussian Mixture Model
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device pci 08.0 off end # Gaussian Mixture Model
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device pci 14.0 on # USB xHCI
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device pci 14.0 on # USB xHCI
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subsystemid 0x1849 0xa131
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subsystemid 0x1849 0xa131
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register "usb2_ports[0]" = "USB2_PORT_MID(OC0)"
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register "usb2_ports[1]" = "USB2_PORT_MID(OC0)"
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register "usb2_ports[2]" = "USB2_PORT_MID(OC4)"
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register "usb2_ports[3]" = "USB2_PORT_MID(OC4)"
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register "usb2_ports[4]" = "USB2_PORT_MID(OC2)"
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register "usb2_ports[5]" = "USB2_PORT_MID(OC2)"
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register "usb2_ports[6]" = "USB2_PORT_MID(OC0)"
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register "usb2_ports[7]" = "USB2_PORT_MID(OC0)"
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register "usb2_ports[8]" = "USB2_PORT_MID(OC0)"
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register "usb2_ports[9]" = "USB2_PORT_MID(OC0)"
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register "usb2_ports[10]" = "USB2_PORT_MID(OC1)"
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register "usb2_ports[11]" = "USB2_PORT_MID(OC1)"
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register "usb2_ports[12]" = "USB2_PORT_MID(OC_SKIP)"
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register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)"
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register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)"
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register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)"
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register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC3)"
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register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)"
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register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC1)"
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register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC1)"
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register "usb3_ports[6]" = "USB3_PORT_DEFAULT(OC_SKIP)"
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register "usb3_ports[7]" = "USB3_PORT_DEFAULT(OC_SKIP)"
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register "usb3_ports[8]" = "USB3_PORT_DEFAULT(OC_SKIP)"
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register "usb3_ports[9]" = "USB3_PORT_DEFAULT(OC_SKIP)"
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end
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end
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device pci 14.1 off end # USB xDCI (OTG)
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device pci 14.1 off end # USB xDCI (OTG)
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device pci 14.2 on # Thermal Subsystem
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device pci 14.2 on # Thermal Subsystem
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@ -266,6 +195,9 @@ chip soc/intel/skylake
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device pci 15.3 off end # I2C #3
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device pci 15.3 off end # I2C #3
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device pci 16.0 on # Management Engine Interface 1
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device pci 16.0 on # Management Engine Interface 1
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subsystemid 0x1849 0xa131
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subsystemid 0x1849 0xa131
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# FIXME: does not match devicetree!
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register "HeciEnabled" = "0"
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end
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end
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device pci 16.1 off end # Management Engine Interface 2
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device pci 16.1 off end # Management Engine Interface 2
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device pci 16.2 off end # Management Engine IDE-R
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device pci 16.2 off end # Management Engine IDE-R
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@ -273,6 +205,22 @@ chip soc/intel/skylake
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device pci 16.4 off end # Management Engine Interface 3
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device pci 16.4 off end # Management Engine Interface 3
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device pci 17.0 on # SATA
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device pci 17.0 on # SATA
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subsystemid 0x1849 0xa102
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subsystemid 0x1849 0xa102
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register "SataSalpSupport" = "1"
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# SATA4 and SATA5 are located in the lower right corner of the board,
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# but they are not populated. This is because the same PCB is used to
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# make boards with better PCHs, which can have up to six SATA ports.
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# However, the H110 PCH only has four SATA ports, which explains why
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# two connectors are missing.
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register "SataPortsEnable" = "{ \
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[0] = 1, \
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[1] = 1, \
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[2] = 1, \
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[3] = 1, \
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[4] = 0, \
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[5] = 0, \
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[6] = 0, \
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[7] = 0, \
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}"
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end
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end
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device pci 19.0 off end # UART #2
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device pci 19.0 off end # UART #2
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device pci 19.1 off end # I2C #5
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device pci 19.1 off end # I2C #5
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@ -281,9 +229,33 @@ chip soc/intel/skylake
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device pci 1c.1 off end # PCI Express Port 2
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device pci 1c.1 off end # PCI Express Port 2
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device pci 1c.2 off end # PCI Express Port 3
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device pci 1c.2 off end # PCI Express Port 3
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device pci 1c.3 off end # PCI Express Port 4
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device pci 1c.3 off end # PCI Express Port 4
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device pci 1c.4 on end # PCI Express Port 5
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device pci 1c.4 on # PCI Express Port 5 - PCIE slot
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device pci 1c.5 on end # PCI Express Port 6
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register "PcieRpEnable[4]" = "1"
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device pci 1c.6 on end # PCI Express Port 7
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register "PcieRpClkReqSupport[4]" = "1"
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register "PcieRpClkReqNumber[4]" = "2"
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register "PcieRpAdvancedErrorReporting[4]" = "1"
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register "PcieRpLtrEnable[4]" = "1"
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register "PcieRpClkSrcNumber[4]" = "2"
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register "PcieRpHotPlug[4]" = "1"
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end
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device pci 1c.5 on # PCI Express Port 6 - Onboard LAN
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register "PcieRpEnable[5]" = "1"
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# Disable CLKREQ#, since onboard LAN is always present
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register "PcieRpClkReqSupport[5]" = "0"
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register "PcieRpAdvancedErrorReporting[5]" = "1"
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register "PcieRpLtrEnable[5]" = "1"
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register "PcieRpClkSrcNumber[5]" = "1"
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end
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device pci 1c.6 on # PCI Express Port 7 - PCIE slot
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register "PcieRpEnable[6]" = "1"
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register "PcieRpClkReqSupport[6]" = "1"
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register "PcieRpClkReqNumber[6]" = "3"
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register "PcieRpAdvancedErrorReporting[6]" = "1"
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register "PcieRpLtrEnable[6]" = "1"
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register "PcieRpClkSrcNumber[6]" = "3"
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register "PcieRpHotPlug[6]" = "1"
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end
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device pci 1c.7 off end # PCI Express Port 8
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device pci 1c.7 off end # PCI Express Port 8
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device pci 1d.0 off end # PCI Express Port 9
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device pci 1d.0 off end # PCI Express Port 9
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device pci 1d.1 off end # PCI Express Port 10
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device pci 1d.1 off end # PCI Express Port 10
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@ -295,10 +267,18 @@ chip soc/intel/skylake
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device pci 1e.3 off end # GSPI #1
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device pci 1e.3 off end # GSPI #1
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device pci 1e.4 off end # eMMC
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device pci 1e.4 off end # eMMC
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device pci 1e.5 off end # SDIO
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device pci 1e.5 off end # SDIO
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device pci 1e.6 off end # SDCard
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device pci 1e.6 off # SDCard
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register "ScsSdCardEnabled" = "0"
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end
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device pci 1f.0 on # LPC bridge
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device pci 1f.0 on # LPC bridge
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subsystemid 0x1849 0x1a43
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subsystemid 0x1849 0x1a43
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# Set @0x280-0x2ff I/O Range for SuperIO HWM
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register "gen1_dec" = "0x007c0281"
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# Set LPC Serial IRQ mode
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register "serirq_mode" = "SERIRQ_CONTINUOUS"
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chip superio/common
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chip superio/common
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device pnp 2e.0 on # passes SIO base addr to SSDT gen
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device pnp 2e.0 on # passes SIO base addr to SSDT gen
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@ -406,7 +386,10 @@ chip soc/intel/skylake
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end # LPC Interface
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end # LPC Interface
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device pci 1f.1 on end # P2SB
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device pci 1f.1 on end # P2SB
|
||||||
device pci 1f.2 on end # Power Management Controller
|
device pci 1f.2 on end # Power Management Controller
|
||||||
device pci 1f.3 on end # Intel HDA
|
device pci 1f.3 on # Intel HDA
|
||||||
|
register "PchHdaVcType" = "Vc1"
|
||||||
|
register "DspEnable" = "0"
|
||||||
|
end
|
||||||
device pci 1f.4 on end # SMBus
|
device pci 1f.4 on end # SMBus
|
||||||
device pci 1f.5 on end # PCH SPI
|
device pci 1f.5 on end # PCH SPI
|
||||||
device pci 1f.6 off end # GbE
|
device pci 1f.6 off end # GbE
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue