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mb/asrock/h110m: Relocate devicetree settings 

Some settings are suspicious, and have been annotated with FIXMEs.

Tested with BUILD_TIMELESS=1, its coreboot.rom does not change.

Change-Id: I7755867cb92745f542a4261db5dd118ca905612b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43919
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Angel Pons 2020-07-26 20:54:09 +02:00 committed by Patrick Georgi
parent 9addda3c41
commit e18cdf4d93
1 changed files with 97 additions and 114 deletions
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211
src/mainboard/asrock/h110m/devicetree.cb
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@ -18,9 +18,6 @@ chip soc/intel/skylake
register "gpe0_dw1" = "GPP_D" register "gpe0_dw1" = "GPP_D"
register "gpe0_dw2" = "GPP_E" register "gpe0_dw2" = "GPP_E"
# Set @0x280-0x2ff I/O Range for SuperIO HWM
register "gen1_dec" = "0x007c0281"
# Enable "Intel Speed Shift Technology" # Enable "Intel Speed Shift Technology"
register "speed_shift_enable" = "1" register "speed_shift_enable" = "1"
@ -28,19 +25,9 @@ chip soc/intel/skylake
register "dptf_enable" = "1" register "dptf_enable" = "1"
# FSP Configuration # FSP Configuration
register "ScsEmmcHs400Enabled" = "0"
register "ScsSdCardEnabled" = "0"
register "HeciEnabled" = "0"
register "SkipExtGfxScan" = "0"
register "PrimaryDisplay" = "Display_PEG" register "PrimaryDisplay" = "Display_PEG"
register "Device4Enable" = "1"
register "SaGv" = "SaGv_Enabled" register "SaGv" = "SaGv_Enabled"
register "PmTimerDisabled" = "0" register "PmTimerDisabled" = "0"
register "DspEnable" = "0"
register "PchHdaVcType" = "Vc1"
# Set LPC Serial IRQ mode
register "serirq_mode" = "SERIRQ_CONTINUOUS"
# Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch # Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch
# SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s # SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s
@ -122,50 +109,6 @@ chip soc/intel/skylake
.voltage_limit = 1520 \ .voltage_limit = 1520 \
}" }"
# USB
register "usb2_ports[0]" = "USB2_PORT_MID(OC0)"
register "usb2_ports[1]" = "USB2_PORT_MID(OC0)"
register "usb2_ports[2]" = "USB2_PORT_MID(OC4)"
register "usb2_ports[3]" = "USB2_PORT_MID(OC4)"
register "usb2_ports[4]" = "USB2_PORT_MID(OC2)"
register "usb2_ports[5]" = "USB2_PORT_MID(OC2)"
register "usb2_ports[6]" = "USB2_PORT_MID(OC0)"
register "usb2_ports[7]" = "USB2_PORT_MID(OC0)"
register "usb2_ports[8]" = "USB2_PORT_MID(OC0)"
register "usb2_ports[9]" = "USB2_PORT_MID(OC0)"
register "usb2_ports[10]" = "USB2_PORT_MID(OC1)"
register "usb2_ports[11]" = "USB2_PORT_MID(OC1)"
register "usb2_ports[12]" = "USB2_PORT_MID(OC_SKIP)"
register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)"
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)"
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)"
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC3)"
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)"
register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC1)"
register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC1)"
register "usb3_ports[6]" = "USB3_PORT_DEFAULT(OC_SKIP)"
register "usb3_ports[7]" = "USB3_PORT_DEFAULT(OC_SKIP)"
register "usb3_ports[8]" = "USB3_PORT_DEFAULT(OC_SKIP)"
register "usb3_ports[9]" = "USB3_PORT_DEFAULT(OC_SKIP)"
# SATA
register "SataSalpSupport" = "1"
# SATA4 and SATA5 are located in the lower right corner of the board,
# but they are not populated. This is because the same PCB is used to
# make boards with better PCHs, which can have up to six SATA ports.
# However, the H110 PCH only has four SATA ports, which explains why
# two connectors are missing.
register "SataPortsEnable" = "{ \
[0] = 1, \
[1] = 1, \
[2] = 1, \
[3] = 1, \
[4] = 0, \
[5] = 0, \
[6] = 0, \
[7] = 0, \
}"
# PCH UART, SPI, I2C # PCH UART, SPI, I2C
register "SerialIoDevMode" = "{ \ register "SerialIoDevMode" = "{ \
[PchSerialIoIndexI2C0] = PchSerialIoDisabled, \ [PchSerialIoIndexI2C0] = PchSerialIoDisabled, \
@ -181,55 +124,6 @@ chip soc/intel/skylake
[PchSerialIoIndexUart2] = PchSerialIoDisabled, \ [PchSerialIoIndexUart2] = PchSerialIoDisabled, \
}" }"
# Set params for PEG 0:1:0
register "Peg0MaxLinkWidth" = "Peg0_x16"
# Configure PCIe clockgen in PCH
# PEG0 uses SRCCLKREQ0 and CLKSRC0
register "PcieRpClkReqSupport[0]" = "1"
register "PcieRpClkReqNumber[0]" = "0"
register "PcieRpClkSrcNumber[0]" = "0"
# Enable Root port 6(x1) for LAN.
register "PcieRpEnable[5]" = "1"
# Disable CLKREQ#, since onboard LAN is always present
register "PcieRpClkReqSupport[5]" = "0"
# Enable Advanced Error Reporting
register "PcieRpAdvancedErrorReporting[5]" = "1"
# Enable Latency Tolerance Reporting Mechanism
register "PcieRpLtrEnable[5]" = "1"
# Use CLK SRC 1
register "PcieRpClkSrcNumber[5]" = "1"
# Enable Root port 5 (x1) for PCIE slot.
register "PcieRpEnable[4]" = "1"
# Enable CLKREQ#
register "PcieRpClkReqSupport[4]" = "1"
# Use SRCCLKREQ2#
register "PcieRpClkReqNumber[4]" = "2"
# Enable Advanced Error Reporting
register "PcieRpAdvancedErrorReporting[4]" = "1"
# Enable Latency Tolerance Reporting Mechanism
register "PcieRpLtrEnable[4]" = "1"
# Use CLK SRC 2
register "PcieRpClkSrcNumber[4]" = "2"
# Use Hot Plug subsystem
register "PcieRpHotPlug[4]" = "1"
# Enable Root port 7(x1) for PCIE slot.
register "PcieRpEnable[6]" = "1"
# Enable CLKREQ#
register "PcieRpClkReqSupport[6]" = "1"
# Use SRCCLKREQ3#
register "PcieRpClkReqNumber[6]" = "3"
# Enable Advanced Error Reporting
register "PcieRpAdvancedErrorReporting[6]" = "1"
# Enable Latency Tolerance Reporting Mechanism
register "PcieRpLtrEnable[6]" = "1"
# Use CLK SRC 3
register "PcieRpClkSrcNumber[6]" = "3"
# Use Hot Plug subsystem
register "PcieRpHotPlug[6]" = "1"
# PL2 override 91W # PL2 override 91W
register "power_limits_config" = "{ register "power_limits_config" = "{
.tdp_pl2_override = 91, .tdp_pl2_override = 91,
@ -247,14 +141,49 @@ chip soc/intel/skylake
end end
device pci 01.0 on # PEG device pci 01.0 on # PEG
subsystemid 0x1849 0x1901 subsystemid 0x1849 0x1901
register "Peg0MaxLinkWidth" = "Peg0_x16"
register "SkipExtGfxScan" = "0"
# Configure PCIe clockgen in PCH
register "PcieRpClkReqSupport[0]" = "1"
register "PcieRpClkReqNumber[0]" = "0"
register "PcieRpClkSrcNumber[0]" = "0"
end end
device pci 02.0 on # Integrated Graphics Device device pci 02.0 on # Integrated Graphics Device
subsystemid 0x1849 0x1912 subsystemid 0x1849 0x1912
end end
device pci 04.0 on end # Thermal Subsystem device pci 04.0 on # Thermal Subsystem
register "Device4Enable" = "1"
end
device pci 08.0 off end # Gaussian Mixture Model device pci 08.0 off end # Gaussian Mixture Model
device pci 14.0 on # USB xHCI device pci 14.0 on # USB xHCI
subsystemid 0x1849 0xa131 subsystemid 0x1849 0xa131
register "usb2_ports[0]" = "USB2_PORT_MID(OC0)"
register "usb2_ports[1]" = "USB2_PORT_MID(OC0)"
register "usb2_ports[2]" = "USB2_PORT_MID(OC4)"
register "usb2_ports[3]" = "USB2_PORT_MID(OC4)"
register "usb2_ports[4]" = "USB2_PORT_MID(OC2)"
register "usb2_ports[5]" = "USB2_PORT_MID(OC2)"
register "usb2_ports[6]" = "USB2_PORT_MID(OC0)"
register "usb2_ports[7]" = "USB2_PORT_MID(OC0)"
register "usb2_ports[8]" = "USB2_PORT_MID(OC0)"
register "usb2_ports[9]" = "USB2_PORT_MID(OC0)"
register "usb2_ports[10]" = "USB2_PORT_MID(OC1)"
register "usb2_ports[11]" = "USB2_PORT_MID(OC1)"
register "usb2_ports[12]" = "USB2_PORT_MID(OC_SKIP)"
register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)"
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)"
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)"
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC3)"
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)"
register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC1)"
register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC1)"
register "usb3_ports[6]" = "USB3_PORT_DEFAULT(OC_SKIP)"
register "usb3_ports[7]" = "USB3_PORT_DEFAULT(OC_SKIP)"
register "usb3_ports[8]" = "USB3_PORT_DEFAULT(OC_SKIP)"
register "usb3_ports[9]" = "USB3_PORT_DEFAULT(OC_SKIP)"
end end
device pci 14.1 off end # USB xDCI (OTG) device pci 14.1 off end # USB xDCI (OTG)
device pci 14.2 on # Thermal Subsystem device pci 14.2 on # Thermal Subsystem
@ -264,8 +193,11 @@ chip soc/intel/skylake
device pci 15.1 off end # I2C #1 device pci 15.1 off end # I2C #1
device pci 15.2 off end # I2C #2 device pci 15.2 off end # I2C #2
device pci 15.3 off end # I2C #3 device pci 15.3 off end # I2C #3
device pci 16.0 on # Management Engine Interface 1 device pci 16.0 on # Management Engine Interface 1
subsystemid 0x1849 0xa131 subsystemid 0x1849 0xa131
# FIXME: does not match devicetree!
register "HeciEnabled" = "0"
end end
device pci 16.1 off end # Management Engine Interface 2 device pci 16.1 off end # Management Engine Interface 2
device pci 16.2 off end # Management Engine IDE-R device pci 16.2 off end # Management Engine IDE-R
@ -273,6 +205,22 @@ chip soc/intel/skylake
device pci 16.4 off end # Management Engine Interface 3 device pci 16.4 off end # Management Engine Interface 3
device pci 17.0 on # SATA device pci 17.0 on # SATA
subsystemid 0x1849 0xa102 subsystemid 0x1849 0xa102
register "SataSalpSupport" = "1"
# SATA4 and SATA5 are located in the lower right corner of the board,
# but they are not populated. This is because the same PCB is used to
# make boards with better PCHs, which can have up to six SATA ports.
# However, the H110 PCH only has four SATA ports, which explains why
# two connectors are missing.
register "SataPortsEnable" = "{ \
[0] = 1, \
[1] = 1, \
[2] = 1, \
[3] = 1, \
[4] = 0, \
[5] = 0, \
[6] = 0, \
[7] = 0, \
}"
end end
device pci 19.0 off end # UART #2 device pci 19.0 off end # UART #2
device pci 19.1 off end # I2C #5 device pci 19.1 off end # I2C #5
@ -281,9 +229,33 @@ chip soc/intel/skylake
device pci 1c.1 off end # PCI Express Port 2 device pci 1c.1 off end # PCI Express Port 2
device pci 1c.2 off end # PCI Express Port 3 device pci 1c.2 off end # PCI Express Port 3
device pci 1c.3 off end # PCI Express Port 4 device pci 1c.3 off end # PCI Express Port 4
device pci 1c.4 on end # PCI Express Port 5 device pci 1c.4 on # PCI Express Port 5 - PCIE slot
device pci 1c.5 on end # PCI Express Port 6 register "PcieRpEnable[4]" = "1"
device pci 1c.6 on end # PCI Express Port 7 register "PcieRpClkReqSupport[4]" = "1"
register "PcieRpClkReqNumber[4]" = "2"
register "PcieRpAdvancedErrorReporting[4]" = "1"
register "PcieRpLtrEnable[4]" = "1"
register "PcieRpClkSrcNumber[4]" = "2"
register "PcieRpHotPlug[4]" = "1"
end
device pci 1c.5 on # PCI Express Port 6 - Onboard LAN
register "PcieRpEnable[5]" = "1"
# Disable CLKREQ#, since onboard LAN is always present
register "PcieRpClkReqSupport[5]" = "0"
register "PcieRpAdvancedErrorReporting[5]" = "1"
register "PcieRpLtrEnable[5]" = "1"
register "PcieRpClkSrcNumber[5]" = "1"
end
device pci 1c.6 on # PCI Express Port 7 - PCIE slot
register "PcieRpEnable[6]" = "1"
register "PcieRpClkReqSupport[6]" = "1"
register "PcieRpClkReqNumber[6]" = "3"
register "PcieRpAdvancedErrorReporting[6]" = "1"
register "PcieRpLtrEnable[6]" = "1"
register "PcieRpClkSrcNumber[6]" = "3"
register "PcieRpHotPlug[6]" = "1"
end
device pci 1c.7 off end # PCI Express Port 8 device pci 1c.7 off end # PCI Express Port 8
device pci 1d.0 off end # PCI Express Port 9 device pci 1d.0 off end # PCI Express Port 9
device pci 1d.1 off end # PCI Express Port 10 device pci 1d.1 off end # PCI Express Port 10
@ -295,10 +267,18 @@ chip soc/intel/skylake
device pci 1e.3 off end # GSPI #1 device pci 1e.3 off end # GSPI #1
device pci 1e.4 off end # eMMC device pci 1e.4 off end # eMMC
device pci 1e.5 off end # SDIO device pci 1e.5 off end # SDIO
device pci 1e.6 off end # SDCard device pci 1e.6 off # SDCard
device pci 1f.0 on # LPC bridge register "ScsSdCardEnabled" = "0"
end
device pci 1f.0 on # LPC bridge
subsystemid 0x1849 0x1a43 subsystemid 0x1849 0x1a43
# Set @0x280-0x2ff I/O Range for SuperIO HWM
register "gen1_dec" = "0x007c0281"
# Set LPC Serial IRQ mode
register "serirq_mode" = "SERIRQ_CONTINUOUS"
chip superio/common chip superio/common
device pnp 2e.0 on # passes SIO base addr to SSDT gen device pnp 2e.0 on # passes SIO base addr to SSDT gen
@ -406,7 +386,10 @@ chip soc/intel/skylake
end # LPC Interface end # LPC Interface
device pci 1f.1 on end # P2SB device pci 1f.1 on end # P2SB
device pci 1f.2 on end # Power Management Controller device pci 1f.2 on end # Power Management Controller
device pci 1f.3 on end # Intel HDA device pci 1f.3 on # Intel HDA
register "PchHdaVcType" = "Vc1"
register "DspEnable" = "0"
end
device pci 1f.4 on end # SMBus device pci 1f.4 on end # SMBus
device pci 1f.5 on end # PCH SPI device pci 1f.5 on end # PCH SPI
device pci 1f.6 off end # GbE device pci 1f.6 off end # GbE