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soc/intel/skylake: Enable CIO depending on devicetree configuration 

Currently, CIO gets enabled by the option Cio2Enable, but this
duplicates the devicetree on/off options. Therefore, depend on
the devicetree for the enablement of the CIO controller.

All corresponding mainboards were checked if the devicetree
configuration matches the Cio2Enable setting, and missing entries
were added.

Change-Id: I65e2cceb65add66e3cb3de7071b1a3cc967ab291
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44032
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Felix Singer 2020-07-29 23:20:52 +02:00 committed by Michael Niewöhner
parent 4d5c4e069c
commit e21866781f
19 changed files with 18 additions and 21 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/mainboard/51nb/x210/devicetree.cb
View File

@ -49,7 +49,6 @@ chip soc/intel/skylake
register "DspEnable" = "0"
register "IoBufferOwnership" = "0"
register "SsicPortEnable" = "0"
register "Cio2Enable" = "0"
register "ScsEmmcHs400Enabled" = "0"
register "PttSwitch" = "0"
register "SkipExtGfxScan" = "1"
@ -125,6 +124,7 @@ chip soc/intel/skylake
device pci 14.0 on end # USB xHCI
device pci 14.1 off end # USB xDCI (OTG)
device pci 14.2 on end # Thermal Subsystem
device pci 14.3 off end # Camera
device pci 16.0 on end # Management Engine Interface 1
device pci 16.1 off end # Management Engine Interface 2
device pci 16.2 off end # Management Engine IDE-R

2
src/mainboard/facebook/monolith/devicetree.cb
View File

@ -39,7 +39,6 @@ chip soc/intel/skylake
register "ScsEmmcHs400Enabled" = "1"
register "SkipExtGfxScan" = "1"
register "SaGv" = "SaGv_Enabled"
register "Cio2Enable" = "0"
register "PmTimerDisabled" = "1"
register "HeciEnabled" = "0"
@ -243,6 +242,7 @@ chip soc/intel/skylake
device pci 14.0 on end # USB xHCI
device pci 14.1 on end # USB xDCI (OTG)
device pci 14.2 on end # Thermal Subsystem
device pci 14.3 off end # Camera
device pci 17.0 on end # SATA
device pci 1c.2 on end # PCI Express Port 3 x1 baseboard WWAN
device pci 1c.5 on end # PCI Express Port 6 x1 baseboard i210

2
src/mainboard/google/eve/devicetree.cb
View File

@ -42,7 +42,6 @@ chip soc/intel/skylake
register "DspEnable" = "1"
register "IoBufferOwnership" = "3"
register "SsicPortEnable" = "0"
register "Cio2Enable" = "0"
register "ScsEmmcHs400Enabled" = "1"
register "PttSwitch" = "0"
register "SkipExtGfxScan" = "1"
@ -295,6 +294,7 @@ chip soc/intel/skylake
end # USB xHCI
device pci 14.1 off end # USB xDCI (OTG)
device pci 14.2 on end # Thermal Subsystem
device pci 14.3 off end # Camera
device pci 15.0 on
chip drivers/i2c/hid
register "generic.hid" = ""WCOM50C1""

2
src/mainboard/google/fizz/variants/baseboard/devicetree.cb
View File

@ -73,7 +73,6 @@ chip soc/intel/skylake
register "DspEnable" = "1"
register "IoBufferOwnership" = "3"
register "SsicPortEnable" = "0"
register "Cio2Enable" = "0"
register "ScsEmmcHs400Enabled" = "0"
register "PttSwitch" = "0"
register "SkipExtGfxScan" = "1"
@ -376,6 +375,7 @@ chip soc/intel/skylake
end # USB xHCI
device pci 14.1 off end # USB xDCI (OTG)
device pci 14.2 on end # Thermal Subsystem
device pci 14.3 off end # Camera
device pci 15.0 on end # I2C #0
device pci 15.1 off end # I2C #1
device pci 15.2 on end # I2C #2

2
src/mainboard/google/glados/devicetree.cb
View File

@ -44,7 +44,6 @@ chip soc/intel/skylake
register "DspEnable" = "1"
register "IoBufferOwnership" = "3"
register "SsicPortEnable" = "0"
register "Cio2Enable" = "0"
register "ScsEmmcHs400Enabled" = "1"
register "PttSwitch" = "0"
register "SkipExtGfxScan" = "1"
@ -104,6 +103,7 @@ chip soc/intel/skylake
device pci 14.0 on end # USB xHCI
device pci 14.1 off end # USB xDCI (OTG)
device pci 14.2 on end # Thermal Subsystem
device pci 14.3 off end # Camera
device pci 15.0 on end # I2C #0
device pci 15.1 on end # I2C #1
device pci 15.2 off end # I2C #2

2
src/mainboard/google/poppy/variants/atlas/devicetree.cb
View File

@ -48,7 +48,6 @@ chip soc/intel/skylake
register "DspEnable" = "1"
register "IoBufferOwnership" = "3"
register "SsicPortEnable" = "0"
register "Cio2Enable" = "1"
register "ScsEmmcHs400Enabled" = "1"
register "PttSwitch" = "0"
register "SkipExtGfxScan" = "1"
@ -274,6 +273,7 @@ chip soc/intel/skylake
end # USB xHCI
device pci 14.1 on end # USB xDCI (OTG)
device pci 14.2 on end # Thermal Subsystem
device pci 14.3 on end # Camera
device pci 15.0 on
chip drivers/i2c/hid
register "generic.hid" = ""ACPI0C50""

2
src/mainboard/google/poppy/variants/baseboard/devicetree.cb
View File

@ -38,7 +38,6 @@ chip soc/intel/skylake
register "DspEnable" = "1"
register "IoBufferOwnership" = "3"
register "SsicPortEnable" = "0"
register "Cio2Enable" = "1"
register "ScsEmmcHs400Enabled" = "1"
register "PttSwitch" = "0"
register "SkipExtGfxScan" = "1"
@ -270,6 +269,7 @@ chip soc/intel/skylake
device pci 14.0 on end # USB xHCI
device pci 14.1 on end # USB xDCI (OTG)
device pci 14.2 on end # Thermal Subsystem
device pci 14.3 on end # Camera
device pci 15.0 on
chip drivers/i2c/generic
register "hid" = ""ELAN0001""

2
src/mainboard/google/poppy/variants/nami/devicetree.cb
View File

@ -37,7 +37,6 @@ chip soc/intel/skylake
register "DspEnable" = "1"
register "IoBufferOwnership" = "3"
register "SsicPortEnable" = "0"
register "Cio2Enable" = "0"
register "ScsEmmcHs400Enabled" = "1"
register "PttSwitch" = "0"
register "SkipExtGfxScan" = "1"
@ -285,6 +284,7 @@ chip soc/intel/skylake
device pci 14.0 on end # USB xHCI
device pci 14.1 on end # USB xDCI (OTG)
device pci 14.2 on end # Thermal Subsystem
device pci 14.3 off end # Camera
device pci 15.0 on
chip drivers/i2c/generic
register "hid" = ""ELAN0001""

2
src/mainboard/google/poppy/variants/nautilus/devicetree.cb
View File

@ -38,7 +38,6 @@ chip soc/intel/skylake
register "DspEnable" = "1"
register "IoBufferOwnership" = "3"
register "SsicPortEnable" = "0"
register "Cio2Enable" = "1"
register "ScsEmmcHs400Enabled" = "1"
register "PttSwitch" = "0"
register "SkipExtGfxScan" = "1"
@ -291,6 +290,7 @@ chip soc/intel/skylake
device pci 14.0 on end # USB xHCI
device pci 14.1 on end # USB xDCI (OTG)
device pci 14.2 on end # Thermal Subsystem
device pci 14.3 on end # Camera
device pci 15.0 on
chip drivers/i2c/hid
register "generic.hid" = ""SYTS7813""

2
src/mainboard/google/poppy/variants/nocturne/devicetree.cb
View File

@ -43,7 +43,6 @@ chip soc/intel/skylake
register "DspEnable" = "1"
register "IoBufferOwnership" = "3"
register "SsicPortEnable" = "0"
register "Cio2Enable" = "1"
register "ScsEmmcHs400Enabled" = "1"
register "PttSwitch" = "0"
register "SkipExtGfxScan" = "1"
@ -298,6 +297,7 @@ chip soc/intel/skylake
end # USB xHCI
device pci 14.1 on end # USB xDCI (OTG)
device pci 14.2 on end # Thermal Subsystem
device pci 14.3 on end # Camera
device pci 15.0 on
chip drivers/i2c/hid
register "generic.hid" = ""WCOM50C1""

2
src/mainboard/google/poppy/variants/rammus/devicetree.cb
View File

@ -48,7 +48,6 @@ chip soc/intel/skylake
register "DspEnable" = "1"
register "IoBufferOwnership" = "3"
register "SsicPortEnable" = "0"
register "Cio2Enable" = "0"
register "ScsEmmcHs400Enabled" = "1"
register "PttSwitch" = "0"
register "SkipExtGfxScan" = "1"
@ -282,6 +281,7 @@ chip soc/intel/skylake
end # USB xHCI
device pci 14.1 on end # USB xDCI (OTG)
device pci 14.2 on end # Thermal Subsystem
device pci 14.3 off end # Camera
device pci 15.0 on
chip drivers/i2c/hid
register "generic.hid" = ""PNP0C50""

2
src/mainboard/google/poppy/variants/soraka/devicetree.cb
View File

@ -38,7 +38,6 @@ chip soc/intel/skylake
register "DspEnable" = "1"
register "IoBufferOwnership" = "3"
register "SsicPortEnable" = "0"
register "Cio2Enable" = "1"
register "ScsEmmcHs400Enabled" = "1"
register "PttSwitch" = "0"
register "SkipExtGfxScan" = "1"
@ -271,6 +270,7 @@ chip soc/intel/skylake
device pci 14.0 on end # USB xHCI
device pci 14.1 on end # USB xDCI (OTG)
device pci 14.2 on end # Thermal Subsystem
device pci 14.3 on end # Camera
device pci 15.0 on
chip drivers/i2c/hid
register "generic.hid" = ""WCOMCOHO""

2
src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb
View File

@ -9,7 +9,6 @@ chip soc/intel/skylake
# FSP Configuration
register "DspEnable" = "1"
register "PmTimerDisabled" = "1"
register "Cio2Enable" = "1"
# VR Settings Configuration for 4 Domains
#+----------------+-------+-------+-------+-------+
@ -121,6 +120,7 @@ chip soc/intel/skylake
device domain 0 on
device pci 05.0 on end # SA IMGU
device pci 14.3 on end # Camera
device pci 1c.0 on end # PCI Express Port 1 x4 SLOT1
device pci 1c.4 on end # PCI Express Port 5 x1 SLOT2/LAN
device pci 1c.5 on end # PCI Express Port 6 x1 SLOT3

2
src/mainboard/libretrend/lt1000/devicetree.cb
View File

@ -50,7 +50,6 @@ chip soc/intel/skylake
register "DspEnable" = "1"
register "IoBufferOwnership" = "0"
register "SsicPortEnable" = "0"
register "Cio2Enable" = "0"
register "ScsEmmcHs400Enabled" = "0"
register "SkipExtGfxScan" = "1"
register "HeciEnabled" = "1"
@ -176,6 +175,7 @@ chip soc/intel/skylake
device pci 14.0 on end # USB xHCI
device pci 14.1 on end # USB xDCI (OTG)
device pci 14.2 on end # Thermal Subsystem
device pci 14.3 off end # Camera
device pci 16.0 on end # Management Engine Interface 1
device pci 16.1 off end # Management Engine Interface 2
device pci 16.2 off end # Management Engine IDE-R

1
src/mainboard/protectli/vault_kbl/devicetree.cb
View File

@ -39,7 +39,6 @@ chip soc/intel/skylake
register "DspEnable" = "0"
register "IoBufferOwnership" = "0"
register "SsicPortEnable" = "0"
register "Cio2Enable" = "0"
register "ScsEmmcHs400Enabled" = "0"
register "SkipExtGfxScan" = "1"
register "HeciEnabled" = "1"

2
src/mainboard/purism/librem_skl/devicetree.cb
View File

@ -55,7 +55,6 @@ chip soc/intel/skylake
register "DspEnable" = "0"
register "IoBufferOwnership" = "0"
register "SsicPortEnable" = "0"
register "Cio2Enable" = "0"
register "ScsEmmcHs400Enabled" = "0"
register "PttSwitch" = "0"
register "SkipExtGfxScan" = "1"
@ -173,6 +172,7 @@ chip soc/intel/skylake
device pci 14.0 on end # USB xHCI
device pci 14.1 on end # USB xDCI (OTG)
device pci 14.2 on end # Thermal Subsystem
device pci 14.3 off end # Camera
device pci 16.0 on end # Management Engine Interface 1
device pci 16.1 off end # Management Engine Interface 2
device pci 16.2 off end # Management Engine IDE-R

2
src/mainboard/razer/blade_stealth_kbl/devicetree.cb
View File

@ -35,7 +35,6 @@ chip soc/intel/skylake
register "DspEnable" = "0"
register "IoBufferOwnership" = "0"
register "SsicPortEnable" = "0"
register "Cio2Enable" = "0"
register "ScsEmmcHs400Enabled" = "0"
register "PttSwitch" = "0"
register "SkipExtGfxScan" = "1"
@ -192,6 +191,7 @@ chip soc/intel/skylake
device pci 14.0 on end # USB xHCI
device pci 14.1 off end # USB xDCI (OTG)
device pci 14.2 on end # Thermal Subsystem
device pci 14.3 off end # Camera
device pci 15.0 on end # I2C Controller #0
device pci 15.1 on
chip drivers/i2c/hid

3
src/soc/intel/skylake/chip.c
View File

@ -229,7 +229,8 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
memcpy(params->SerialIoDevMode, config->SerialIoDevMode,
sizeof(params->SerialIoDevMode));
params->PchCio2Enable = config->Cio2Enable;
dev = pcidev_path_on_root(PCH_DEVFN_CIO);
params->PchCio2Enable = dev && dev->enabled;
dev = pcidev_path_on_root(SA_DEVFN_IMGU);
params->SaImguEnable = dev && dev->enabled;

3
src/soc/intel/skylake/chip.h
View File

@ -300,9 +300,6 @@ struct soc_intel_skylake_config {
/* Bus voltage level, default is 3.3V */
enum skylake_i2c_voltage i2c_voltage[CONFIG_SOC_INTEL_I2C_DEV_MAX];
/* Camera */
u8 Cio2Enable;
/* eMMC and SD */
u8 ScsEmmcHs400Enabled;
u8 EmmcHs400DllNeed;