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nb/intel/ironlake: Drop `pci_mmio_size` 

There's no good reason to use values smaller than 2 GiB here. Well, it
increases available DRAM in 32-bit space. However, as this is a 64-bit
platform, it's highly unlikely that 32-bit limitations would cause any
issues anymore. It's more likely to have the allocator give up because
memory-mapped resources in 32-bit space don't fit within the specified
MMIO size, which can easily occur when using a discrete graphics card.

Change-Id: I6cdce5f56bc94cca7065ee3e38af60d1de66e45c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52070
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Angel Pons 2021-04-02 22:42:53 +02:00
parent 83e319d6f5
commit e24f97c081
5 changed files with 1 additions and 29 deletions
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2
src/mainboard/lenovo/t410/devicetree.cb
View File

@ -23,8 +23,6 @@ chip northbridge/intel/ironlake
end end
end end
register "pci_mmio_size" = "2048"
device domain 0 on device domain 0 on
device pci 00.0 on # Host bridge device pci 00.0 on # Host bridge
subsystemid 0x17aa 0x2193 subsystemid 0x17aa 0x2193

2
src/mainboard/lenovo/x201/devicetree.cb
View File

@ -24,8 +24,6 @@ chip northbridge/intel/ironlake
end end
end end
register "pci_mmio_size" = "1024"
device domain 0 on device domain 0 on
device pci 00.0 on # Host bridge device pci 00.0 on # Host bridge
subsystemid 0x17aa 0x2193 subsystemid 0x17aa 0x2193

2
src/mainboard/packardbell/ms2290/devicetree.cb
View File

@ -24,8 +24,6 @@ chip northbridge/intel/ironlake
end end
end end
register "pci_mmio_size" = "2048"
device domain 0 on device domain 0 on
device pci 00.0 on # Host bridge device pci 00.0 on # Host bridge
subsystemid 0x1025 0x0379 subsystemid 0x1025 0x0379

5
src/northbridge/intel/ironlake/chip.h
View File

@ -34,11 +34,6 @@ struct northbridge_intel_ironlake_config {
u32 gpu_pch_backlight; /* PCH Backlight PWM value */ u32 gpu_pch_backlight; /* PCH Backlight PWM value */
struct i915_gpu_controller_info gfx; struct i915_gpu_controller_info gfx;
/*
* Maximum PCI mmio size in MiB.
*/
u16 pci_mmio_size;
}; };
#endif /* NORTHBRIDGE_INTEL_IRONLAKE_CHIP_H */ #endif /* NORTHBRIDGE_INTEL_IRONLAKE_CHIP_H */

19
src/northbridge/intel/ironlake/raminit.c
View File

@ -1273,23 +1273,6 @@ static void program_board_delay(struct raminfo *info)
} }
#define DEFAULT_PCI_MMIO_SIZE 2048 #define DEFAULT_PCI_MMIO_SIZE 2048
#define HOST_BRIDGE PCI_DEVFN(0, 0)
static unsigned int get_mmio_size(void)
{
const struct device *dev;
const struct northbridge_intel_ironlake_config *cfg = NULL;
dev = pcidev_path_on_root(HOST_BRIDGE);
if (dev)
cfg = dev->chip_info;
/* If this is zero, it just means devicetree.cb didn't set it */
if (!cfg || cfg->pci_mmio_size == 0)
return DEFAULT_PCI_MMIO_SIZE;
else
return cfg->pci_mmio_size;
}
static void program_total_memory_map(struct raminfo *info) static void program_total_memory_map(struct raminfo *info)
{ {
@ -1323,7 +1306,7 @@ static void program_total_memory_map(struct raminfo *info)
uma_size_gtt = uma_sizes_gtt[(t >> 8) & 0xF]; uma_size_gtt = uma_sizes_gtt[(t >> 8) & 0xF];
} }
mmio_size = get_mmio_size(); mmio_size = DEFAULT_PCI_MMIO_SIZE;
tom = info->total_memory_mb; tom = info->total_memory_mb;
if (tom == 4096) if (tom == 4096)