mb/google/puff: Update i2c[2] and i2c[3] rise and fall times
BRANCH=none BUG=b:158713330 TEST=Flashing the LSPCON firmware works Change-Id: Ib371f6954115145047c70cfd25262026cce087fd Signed-off-by: Sam McNally <sammc@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42275 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
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@ -158,13 +158,13 @@ chip soc/intel/cannonlake
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},
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.i2c[2] = {
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.speed = I2C_SPEED_FAST,
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.rise_time_ns = 0,
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.fall_time_ns = 0,
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.rise_time_ns = 60,
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.fall_time_ns = 60,
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},
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.i2c[3] = {
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.speed = I2C_SPEED_FAST,
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.rise_time_ns = 0,
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.fall_time_ns = 0,
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.rise_time_ns = 60,
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.fall_time_ns = 60,
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},
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.i2c[4] = {
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.speed = I2C_SPEED_FAST,
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@ -158,13 +158,13 @@ chip soc/intel/cannonlake
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},
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.i2c[2] = {
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.speed = I2C_SPEED_FAST,
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.rise_time_ns = 0,
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.fall_time_ns = 0,
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.rise_time_ns = 60,
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.fall_time_ns = 60,
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},
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.i2c[3] = {
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.speed = I2C_SPEED_FAST,
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.rise_time_ns = 0,
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.fall_time_ns = 0,
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.rise_time_ns = 60,
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.fall_time_ns = 60,
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},
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.i2c[4] = {
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.speed = I2C_SPEED_FAST,
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@ -161,13 +161,13 @@ chip soc/intel/cannonlake
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},
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.i2c[2] = {
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.speed = I2C_SPEED_FAST,
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.rise_time_ns = 0,
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.fall_time_ns = 0,
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.rise_time_ns = 60,
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.fall_time_ns = 60,
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},
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.i2c[3] = {
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.speed = I2C_SPEED_FAST,
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.rise_time_ns = 0,
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.fall_time_ns = 0,
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.rise_time_ns = 60,
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.fall_time_ns = 60,
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},
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.i2c[4] = {
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.speed = I2C_SPEED_FAST,
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@ -161,13 +161,13 @@ chip soc/intel/cannonlake
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},
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.i2c[2] = {
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.speed = I2C_SPEED_FAST,
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.rise_time_ns = 0,
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.fall_time_ns = 0,
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.rise_time_ns = 60,
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.fall_time_ns = 60,
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},
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.i2c[3] = {
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.speed = I2C_SPEED_FAST,
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.rise_time_ns = 0,
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.fall_time_ns = 0,
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.rise_time_ns = 60,
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.fall_time_ns = 60,
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},
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.i2c[4] = {
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.speed = I2C_SPEED_FAST,
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