northbridge/amd/amdmct: Fix hang on boot due to invalid array access
Change-Id: I47755caf7d2ff59463c817e739f9cb2ddd367c18 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/11989 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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@ -333,7 +333,7 @@ static void mctGet_MaxLoadFreq(struct DCTStatStruc *pDCTstat)
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#if (CONFIG_DIMM_SUPPORT & 0x000F)==0x0005 /* AMD_FAM10_DDR3 */
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#if (CONFIG_DIMM_SUPPORT & 0x000F)==0x0005 /* AMD_FAM10_DDR3 */
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uint8_t dimm;
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uint8_t dimm;
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for (i = 0; i < 15; i = i + 2) {
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for (i = 0; i < MAX_DIMMS_SUPPORTED; i = i + 2) {
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if (pDCTstat->DIMMValid & (1 << i))
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if (pDCTstat->DIMMValid & (1 << i))
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ch1_voltage |= pDCTstat->DimmConfiguredVoltage[i];
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ch1_voltage |= pDCTstat->DimmConfiguredVoltage[i];
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if (pDCTstat->DIMMValid & (1 << (i + 1)))
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if (pDCTstat->DIMMValid & (1 << (i + 1)))
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@ -343,7 +343,7 @@ static void mctGet_MaxLoadFreq(struct DCTStatStruc *pDCTstat)
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for (i = 0; i < 2; i++) {
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for (i = 0; i < 2; i++) {
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sDCTStruct *pDCTData = pDCTstat->C_DCTPtr[i];
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sDCTStruct *pDCTData = pDCTstat->C_DCTPtr[i];
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highest_rank_count[i] = 0x0;
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highest_rank_count[i] = 0x0;
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for (dimm = 0; dimm < 8; dimm++) {
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for (dimm = 0; dimm < MAX_DIMMS_SUPPORTED; dimm++) {
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if (pDCTData->DimmRanks[dimm] > highest_rank_count[i])
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if (pDCTData->DimmRanks[dimm] > highest_rank_count[i])
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highest_rank_count[i] = pDCTData->DimmRanks[dimm];
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highest_rank_count[i] = pDCTData->DimmRanks[dimm];
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}
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}
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