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rambi: configure USBPHY_COMPBG by the setting in devicetree.cb 

USBPHY_COMPBG needs to be configured by project

BUG=chrome-os-partner:30690
BRANCH=none
TEST=emerge-rambi coreboot without problem
     checked the USBPHY_COMPBG is configured properly
CQ-DEPEND=CL:208557

Original-Change-Id: I8f2714644e1ef5d790d7ef1f574ebb998abbdac6
Original-Signed-off-by: Kane Chen <kane.chen@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/208731
Original-Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
(cherry picked from commit 1e9aeebb769e30940175cf3c38afe7ecfa69b5b4)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I28aa445ccb4506db65784e30253dd16161b2bc75
Reviewed-on: http://review.coreboot.org/8217
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Kane Chen 2014-07-17 11:31:57 -07:00 committed by Marc Jones
parent 314c4c3ed6
commit e381544292
1 changed files with 1 additions and 0 deletions
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1
src/mainboard/google/rambi/devicetree.cb
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@ -22,6 +22,7 @@ chip soc/intel/baytrail
register "usb2_per_port_rcomp_hs_pullup2" = "0x01004015" register "usb2_per_port_rcomp_hs_pullup2" = "0x01004015"
register "usb2_per_port_lane3" = "0x00049a09" register "usb2_per_port_lane3" = "0x00049a09"
register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d" register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d"
register "usb2_comp_bg" = "0x4700"
# LPE audio codec settings # LPE audio codec settings
register "lpe_codec_clk_freq" = "25" # 25MHz clock register "lpe_codec_clk_freq" = "25" # 25MHz clock