mb/intel/coffeelake_rvp: Add whiskey lake rvp
Add new mainboard variant of whiskey lake rvp, which is primary validation platform for whiskey lake silicon, support socket DDR4 memory module. BUG=N/A TEST=Build and flash, confirm boot up into kernel on whiskey lake rvp platform. Change-Id: I4a5e8a9ec76d5e55e55ef9bf968825c17fbe9816 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/27628 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Lijian Zhao
Martin Roth
parent
5b5656565b
commit
e391cbff7f
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@ -1,4 +1,4 @@
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if BOARD_INTEL_COFFEELAKE_RVPU || BOARD_INTEL_COFFEELAKE_RVP11
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if BOARD_INTEL_COFFEELAKE_RVP11 || BOARD_INTEL_COFFEELAKE_RVPU || BOARD_INTEL_WHISKEYLAKE_RVP
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config BOARD_SPECIFIC_OPTIONS
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def_bool y
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@ -22,6 +22,7 @@ config VARIANT_DIR
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string
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default "cfl_u" if BOARD_INTEL_COFFEELAKE_RVPU
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default "cfl_h" if BOARD_INTEL_COFFEELAKE_RVP11
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default "whl_u" if BOARD_INTEL_WHISKEYLAKE_RVP
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config MAINBOARD_PART_NUMBER
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string
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@ -4,3 +4,5 @@ config BOARD_INTEL_COFFEELAKE_RVPU
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bool "-> Coffeelake U SO-DIMM DDR4 RVP"
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config BOARD_INTEL_COFFEELAKE_RVP11
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bool "-> Coffeelake H SO-DIMM DDR4 RVP11"
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config BOARD_INTEL_WHISKEYLAKE_RVP
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bool "-> Whiskeylake U DDR4 RVP"
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@ -2,7 +2,7 @@
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2016 Google Inc.
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* Copyright (C) 2017-20188 Intel Corp.
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* Copyright (C) 2017-2018 Intel Corp.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -17,7 +17,6 @@
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#include <baseboard/variants.h>
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#include <commonlib/helpers.h>
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#if IS_ENABLED(CONFIG_BOARD_INTEL_COFFEELAKE_RVPU)
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static const struct pad_config gpio_table[] = {
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/* GPPC */
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/* A0 : RCINB_TIME_SYNC_1 */
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@ -284,14 +283,7 @@ static const struct pad_config gpio_table[] = {
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/* GPD-9 : SLP_WLANB */
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/* GPD-10 : SLP_5B */
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/* GPD_11 : LANPHYPC */
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};
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#elif IS_ENABLED(CONFIG_BOARD_INTEL_COFFEELAKE_RVP11)
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static const struct pad_config gpio_table[] = {
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};
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#endif
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/* Early pad configuration in bootblock */
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static const struct pad_config early_gpio_table[] = {
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@ -0,0 +1,139 @@
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chip soc/intel/cannonlake
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device cpu_cluster 0 on
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device lapic 0 on end
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end
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# FSP configuration
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register "SaGv" = "3"
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register "SmbusEnable" = "1"
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register "ScsEmmcEnabled" = "1"
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register "ScsEmmcHs400Enabled" = "1"
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register "ScsSdCardEnabled" = "1"
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register "HeciEnabled" = "1"
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register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)"
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register "usb2_ports[1]" = "USB2_PORT_MID(OC0)"
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register "usb2_ports[2]" = "USB2_PORT_MID(OC0)"
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register "usb2_ports[3]" = "USB2_PORT_MID(OC0)"
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register "usb2_ports[4]" = "USB2_PORT_MID(OC0)"
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register "usb2_ports[5]" = "USB2_PORT_MID(OC0)"
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register "usb2_ports[6]" = "USB2_PORT_MID(OC0)"
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register "usb2_ports[7]" = "USB2_PORT_MID(OC0)"
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register "usb2_ports[8]" = "USB2_PORT_MID(OC0)"
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register "usb2_ports[9]" = "USB2_PORT_MID(OC0)"
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register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)"
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register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)"
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register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)"
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register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC0)"
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register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)"
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register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC0)"
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register "SataEnable" = "1"
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register "SataSalpSupport" = "1"
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register "SataPortsEnable[0]" = "1"
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register "SataPortsEnable[1]" = "1"
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register "SataPortsEnable[2]" = "1"
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register "SataPortsEnable[3]" = "1"
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register "SataPortsEnable[4]" = "1"
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register "SataPortsEnable[5]" = "1"
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register "SataPortsEnable[6]" = "1"
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register "SataPortsEnable[7]" = "1"
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register "PchHdaDspEnable" = "1"
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register "PchHdaAudioLinkHda" = "1"
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register "PcieRpEnable[0]" = "1"
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register "PcieRpEnable[1]" = "1"
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register "PcieRpEnable[2]" = "1"
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register "PcieRpEnable[3]" = "1"
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register "PcieRpEnable[4]" = "1"
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register "PcieRpEnable[5]" = "1"
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register "PcieRpEnable[6]" = "1"
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register "PcieRpEnable[7]" = "1"
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register "PcieRpEnable[8]" = "1"
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register "PcieRpEnable[9]" = "1"
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register "PcieRpEnable[10]" = "1"
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register "PcieRpEnable[11]" = "1"
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register "PcieRpEnable[12]" = "1"
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register "PcieRpEnable[13]" = "1"
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register "PcieRpEnable[14]" = "1"
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register "PcieRpEnable[15]" = "1"
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register "PcieClkSrcUsage[0]" = "1"
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register "PcieClkSrcUsage[1]" = "8"
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register "PcieClkSrcUsage[2]" = "PCIE_CLK_LAN"
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register "PcieClkSrcUsage[3]" = "13"
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register "PcieClkSrcUsage[4]" = "4"
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register "PcieClkSrcUsage[5]" = "14"
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register "PcieClkSrcClkReq[0]" = "0"
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register "PcieClkSrcClkReq[1]" = "1"
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register "PcieClkSrcClkReq[2]" = "2"
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register "PcieClkSrcClkReq[3]" = "3"
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register "PcieClkSrcClkReq[4]" = "4"
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register "PcieClkSrcClkReq[5]" = "5"
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# Enable "Intel Speed Shift Technology"
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register "speed_shift_enable" = "1"
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# GPIO for SD card detect
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register "sdcard_cd_gpio" = "GPP_G5"
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device domain 0 on
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device pci 00.0 on end # Host Bridge
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device pci 02.0 on end # Integrated Graphics Device
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device pci 04.0 on end # SA Thermal device
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device pci 12.0 on end # Thermal Subsystem
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device pci 12.5 off end # UFS SCS
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device pci 12.6 off end # GSPI #2
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device pci 14.0 on end # USB xHCI
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device pci 14.1 off end # USB xDCI (OTG)
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device pci 14.3 on end # CNVi wifi
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device pci 14.5 on end # SDCard
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device pci 15.0 on end # I2C #0
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device pci 15.1 on end # I2C #1
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device pci 15.2 off end # I2C #2
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device pci 15.3 off end # I2C #3
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device pci 16.0 on end # Management Engine Interface 1
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device pci 16.1 off end # Management Engine Interface 2
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device pci 16.2 off end # Management Engine IDE-R
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device pci 16.3 off end # Management Engine KT Redirection
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device pci 16.4 off end # Management Engine Interface 3
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device pci 16.5 off end # Management Engine Interface 4
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device pci 17.0 on end # SATA
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device pci 19.0 on end # I2C #4
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device pci 19.1 off end # I2C #5
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device pci 19.2 on end # UART #2
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device pci 1a.0 on end # eMMC
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device pci 1c.0 on end # PCI Express Port 1 x4 SLOT1
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device pci 1c.4 on end # PCI Express Port 5 x1 SLOT2/LAN
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device pci 1c.5 off end # PCI Express Port 6
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device pci 1c.6 off end # PCI Express Port 7
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device pci 1c.7 off end # PCI Express Port 8
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device pci 1d.0 on end # PCI Express Port 9
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device pci 1d.1 off end # PCI Express Port 10
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device pci 1d.2 off end # PCI Express Port 11
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device pci 1d.3 off end # PCI Express Port 12
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device pci 1d.4 off end # PCI Express Port 13
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device pci 1d.5 off end # PCI Express Port 14
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device pci 1d.6 off end # PCI Express Port 15
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device pci 1d.7 off end # PCI Express Port 16
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device pci 1e.0 on end # UART #0
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device pci 1e.1 off end # UART #1
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device pci 1e.2 off end # GSPI #0
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device pci 1e.3 off end # GSPI #1
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device pci 1f.0 on
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chip drivers/pc80/tpm
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device pnp 0c31.0 on end
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end
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end # LPC Interface
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device pci 1f.1 on end # P2SB
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device pci 1f.2 on end # Power Management Controller
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device pci 1f.3 on end # Intel HDA
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device pci 1f.4 on end # SMBus
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device pci 1f.5 on end # PCH SPI
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device pci 1f.6 off end # GbE
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end
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end
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@ -0,0 +1,21 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2018 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
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* GNU General Public License for more details.
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*/
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#ifndef __MAINBOARD_GPIO_H__
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#define __MAINBOARD_GPIO_H__
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#include <baseboard/gpio.h>
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#endif /* __MAINBOARD_GPIO_H__ */
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