soc/intel/broadwell: Rework IGD's CDClk selection
CDClk selection was wrong in some corner cases (e.g. ULX SKUs) and,
for Broadwell, never took the devicetree config into account.
Rewrite the selection with the following in mind:
o cpu_is_ult() might return `true` for ULX SKUs, too,
o ULX and Broadwell-ULT SKUs can be `overclocked` with additional
cooling, so leave that as devicetree option.
For Haswell, the following frequency selections are valid:
o ULX: 337.5MHz by default, 450MHz optional
o ULT: 450MHz only (maybe 337.5MHz too, documentation varies,
it wasn't selectable before either)
o others: 540MHz by default, 450MHz optional
For Broadwell:
o ULX: 450MHz by default, 337.5MHz / 540MHz optional
o ULT: 540MHz by default, 337.5MHz / 450MHz / 675MHz optional
o others: 667MHz by default, 337.5MHz / 450MHz / 540MHz optional
Side effects: A too high setting in the devicetree results in the
highest possible frequency now, Haswell non-ULT/ULX defaults to 540MHz
instead of 450MHz.
Change-Id: Iec12752f2a47bf4a5ae6077c75790eae9378c1b2
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/17768
Tested-by: build bot (Jenkins)
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
This commit is contained in:
Nico Huber
parent
589fc3473e
commit
e392f414cd
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@ -33,11 +33,14 @@
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#include <vboot/vbnv.h>
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#include <soc/igd.h>
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#define GT_RETRY 1000
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#define GT_CDCLK_337 0
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#define GT_CDCLK_450 1
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#define GT_CDCLK_540 2
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#define GT_CDCLK_675 3
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#define GT_RETRY 1000
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enum {
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GT_CDCLK_DEFAULT = 0,
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GT_CDCLK_337,
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GT_CDCLK_450,
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GT_CDCLK_540,
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GT_CDCLK_675,
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};
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static u32 reg_em4;
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static u32 reg_em5;
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@ -338,81 +341,49 @@ static void igd_setup_panel(struct device *dev)
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}
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}
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static void igd_cdclk_init_haswell(struct device *dev)
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static int igd_get_cdclk_haswell(u32 *const cdsel, int *const inform_pc,
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struct device *const dev)
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{
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config_t *conf = dev->chip_info;
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const config_t *const conf = dev->chip_info;
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int cdclk = conf->cdclk;
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int devid = pci_read_config16(dev, PCI_DEVICE_ID);
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int gpu_is_ulx = 0;
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u32 dpdiv, lpcll;
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/* Check for ULX GT1 or GT2 */
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if (devid == 0x0a0e || devid == 0x0a1e)
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gpu_is_ulx = 1;
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const int devid = pci_read_config16(dev, PCI_DEVICE_ID);
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const int gpu_is_ulx = devid == IGD_HASWELL_ULX_GT1 ||
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devid == IGD_HASWELL_ULX_GT2;
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/* 675MHz is not supported on haswell */
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if (cdclk == GT_CDCLK_675)
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cdclk = GT_CDCLK_337;
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/* If CD clock is fixed or ULT then set to 450MHz */
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if ((gtt_read(0x42014) & 0x1000000) || cpu_is_ult())
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/* Check for fixed fused clock */
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if (gtt_read(0x42014) & 1 << 24)
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cdclk = GT_CDCLK_450;
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/* 540MHz is not supported on ULX */
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if (gpu_is_ulx && cdclk == GT_CDCLK_540)
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/*
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* ULX defaults to 337MHz with possible override for 450MHz
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* ULT is fixed at 450MHz
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* others default to 540MHz with possible override for 450MHz
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*/
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if (gpu_is_ulx && cdclk <= GT_CDCLK_337)
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cdclk = GT_CDCLK_337;
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/* 337.5MHz is not supported on non-ULT/ULX */
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if (!gpu_is_ulx && !cpu_is_ult() && cdclk == GT_CDCLK_337)
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else if (gpu_is_ulx || cpu_is_ult() ||
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cdclk == GT_CDCLK_337 || cdclk == GT_CDCLK_450)
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cdclk = GT_CDCLK_450;
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else
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cdclk = GT_CDCLK_540;
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/* Set variables based on CD Clock setting */
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switch (cdclk) {
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case GT_CDCLK_337:
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dpdiv = 169;
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lpcll = (1 << 26);
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reg_em4 = 16;
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reg_em5 = 225;
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break;
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case GT_CDCLK_450:
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dpdiv = 225;
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lpcll = 0;
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reg_em4 = 4;
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reg_em5 = 75;
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break;
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case GT_CDCLK_540:
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dpdiv = 270;
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lpcll = (1 << 26);
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reg_em4 = 4;
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reg_em5 = 90;
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break;
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default:
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return;
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}
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/* Set LPCLL_CTL CD Clock Frequency Select */
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gtt_rmw(0x130040, 0xf3ffffff, lpcll);
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/* ULX: Inform power controller of selected frequency */
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if (gpu_is_ulx) {
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if (cdclk == GT_CDCLK_450)
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gtt_write(0x138128, 0x00000000); /* 450MHz */
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else
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gtt_write(0x138128, 0x00000001); /* 337.5MHz */
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gtt_write(0x13812c, 0x00000000);
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gtt_write(0x138124, 0x80000017);
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}
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/* Set CPU DP AUX 2X bit clock dividers */
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gtt_rmw(0x64010, 0xfffff800, dpdiv);
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gtt_rmw(0x64810, 0xfffff800, dpdiv);
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*cdsel = cdclk != GT_CDCLK_450;
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*inform_pc = gpu_is_ulx;
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return cdclk;
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}
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static void igd_cdclk_init_broadwell(struct device *dev)
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static int igd_get_cdclk_broadwell(u32 *const cdsel, int *const inform_pc,
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struct device *const dev)
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{
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config_t *conf = dev->chip_info;
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static const u32 cdsel_by_cdclk[] = { 0, 2, 0, 1, 3 };
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const config_t *const conf = dev->chip_info;
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int cdclk = conf->cdclk;
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u32 dpdiv, lpcll, pwctl, cdset;
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/* Check for ULX */
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const int devid = pci_read_config16(dev, PCI_DEVICE_ID);
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const int gpu_is_ulx = devid == IGD_BROADWELL_Y_GT2;
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/* Inform power controller of upcoming frequency change */
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gtt_write(0x138128, 0);
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@ -420,54 +391,69 @@ static void igd_cdclk_init_broadwell(struct device *dev)
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gtt_write(0x138124, 0x80000018);
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/* Poll GT driver mailbox for run/busy clear */
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if (!gtt_poll(0x138124, (1 << 31), (0 << 31)))
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cdclk = GT_CDCLK_450;
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if (gtt_read(0x42014) & 0x1000000) {
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/* If CD clock is fixed then set to 450MHz */
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cdclk = GT_CDCLK_450;
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if (gtt_poll(0x138124, (1 << 31), (0 << 31))) {
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*inform_pc = 1;
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} else {
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/* Program CD clock to highest supported freq */
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if (cpu_is_ult())
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cdclk = GT_CDCLK_540;
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else
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cdclk = GT_CDCLK_675;
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cdclk = GT_CDCLK_450;
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*inform_pc = 0;
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}
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/* CD clock frequency 675MHz not supported on ULT */
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if (cpu_is_ult() && cdclk == GT_CDCLK_675)
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/* Check for fixed fused clock */
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if (gtt_read(0x42014) & 1 << 24)
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cdclk = GT_CDCLK_450;
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/*
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* ULX defaults to 450MHz with possible override up to 540MHz
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* ULT defaults to 540MHz with possible override up to 675MHz
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* others default to 675MHz with possible override for lower freqs
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*/
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if (cdclk == GT_CDCLK_337)
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cdclk = GT_CDCLK_337;
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else if (cdclk == GT_CDCLK_450 ||
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(gpu_is_ulx && cdclk == GT_CDCLK_DEFAULT))
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cdclk = GT_CDCLK_450;
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else if (cdclk == GT_CDCLK_540 || gpu_is_ulx ||
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(cpu_is_ult() && cdclk == GT_CDCLK_DEFAULT))
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cdclk = GT_CDCLK_540;
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else
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cdclk = GT_CDCLK_675;
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*cdsel = cdsel_by_cdclk[cdclk];
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return cdclk;
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}
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static void igd_cdclk_init(struct device *dev, const int is_broadwell)
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{
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u32 dpdiv, cdsel, cdval;
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int cdclk, inform_pc;
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if (is_broadwell)
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cdclk = igd_get_cdclk_broadwell(&cdsel, &inform_pc, dev);
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else
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cdclk = igd_get_cdclk_haswell(&cdsel, &inform_pc, dev);
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/* Set variables based on CD Clock setting */
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switch (cdclk) {
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case GT_CDCLK_337:
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cdset = 337;
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lpcll = (1 << 27);
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pwctl = 2;
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cdval = 337;
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dpdiv = 169;
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reg_em4 = 16;
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reg_em5 = 225;
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break;
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case GT_CDCLK_450:
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cdset = 449;
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lpcll = 0;
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pwctl = 0;
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cdval = 449;
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dpdiv = 225;
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reg_em4 = 4;
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reg_em5 = 75;
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break;
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case GT_CDCLK_540:
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cdset = 539;
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lpcll = (1 << 26);
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pwctl = 1;
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cdval = 539;
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dpdiv = 270;
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reg_em4 = 4;
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reg_em5 = 90;
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break;
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case GT_CDCLK_675:
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cdset = 674;
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lpcll = (1 << 26) | (1 << 27);
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pwctl = 3;
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cdval = 674;
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dpdiv = 338;
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reg_em4 = 8;
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reg_em5 = 225;
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@ -476,15 +462,17 @@ static void igd_cdclk_init_broadwell(struct device *dev)
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}
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/* Set LPCLL_CTL CD Clock Frequency Select */
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gtt_rmw(0x130040, 0xf3ffffff, lpcll);
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gtt_rmw(0x130040, 0xf3ffffff, cdsel << 26);
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/* Inform power controller of selected frequency */
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gtt_write(0x138128, pwctl);
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gtt_write(0x13812c, 0);
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gtt_write(0x138124, 0x80000017);
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if (inform_pc) {
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/* Inform power controller of selected frequency */
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gtt_write(0x138128, cdsel);
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gtt_write(0x13812c, 0);
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gtt_write(0x138124, 0x80000017);
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}
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/* Program CD Clock Frequency */
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gtt_rmw(0x46200, 0xfffffc00, cdset);
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gtt_rmw(0x46200, 0xfffffc00, cdval);
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/* Set CPU DP AUX 2X bit clock dividers */
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gtt_rmw(0x64010, 0xfffff800, dpdiv);
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@ -541,11 +529,10 @@ static void igd_init(struct device *dev)
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pci_dev_init(dev);
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/* Late init steps */
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igd_cdclk_init(dev, is_broadwell);
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if (is_broadwell) {
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igd_cdclk_init_broadwell(dev);
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reg_script_run_on_dev(dev, broadwell_late_init_script);
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} else {
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igd_cdclk_init_haswell(dev);
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reg_script_run_on_dev(dev, haswell_late_init_script);
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}
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@ -24,6 +24,8 @@
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#define IGD_HASWELL_ULT_GT1 0x0a06
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#define IGD_HASWELL_ULT_GT2 0x0a16
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#define IGD_HASWELL_ULT_GT3 0x0a26
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#define IGD_HASWELL_ULX_GT1 0x0a0e
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#define IGD_HASWELL_ULX_GT2 0x0a1e
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#define IGD_BROADWELL_U_GT1 0x1606
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#define IGD_BROADWELL_U_GT2 0x1616
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#define IGD_BROADWELL_U_GT3_15W 0x1626
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