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Nico Huber e392f414cd soc/intel/broadwell: Rework IGD's CDClk selection
CDClk selection was wrong in some corner cases (e.g. ULX SKUs) and,
for Broadwell, never took the devicetree config into account.

Rewrite the selection with the following in mind:

  o cpu_is_ult() might return `true` for ULX SKUs, too,

  o ULX and Broadwell-ULT SKUs can be `overclocked` with additional
    cooling, so leave that as devicetree option.

For Haswell, the following frequency selections are valid:

  o ULX: 337.5MHz by default, 450MHz optional
  o ULT: 450MHz only (maybe 337.5MHz too, documentation varies,
                      it wasn't selectable before either)
  o others: 540MHz by default, 450MHz optional

For Broadwell:

  o ULX: 450MHz by default, 337.5MHz / 540MHz optional
  o ULT: 540MHz by default, 337.5MHz / 450MHz / 675MHz optional
  o others: 667MHz by default, 337.5MHz / 450MHz / 540MHz optional

Side effects: A too high setting in the devicetree results in the
highest possible frequency now, Haswell non-ULT/ULX defaults to 540MHz
instead of 450MHz.

Change-Id: Iec12752f2a47bf4a5ae6077c75790eae9378c1b2
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/17768
Tested-by: build bot (Jenkins)
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-03-10 17:39:46 +01:00
3rdparty 3rdparty: update arm-trusted-firmware submodule 2017-01-12 18:38:26 +01:00
Documentation arch/x86/acpigen: Provide helper functions for enabling/disabling GPIO 2017-02-22 22:19:29 +01:00
configs configs/builder: Remove pre-defined VGA bios file 2017-01-20 17:37:19 +01:00
payloads libpayload-x86: Enable SSE and FPU when present 2017-03-08 04:44:12 +01:00
src soc/intel/broadwell: Rework IGD's CDClk selection 2017-03-10 17:39:46 +01:00
util ifdtool: Add SPI_FREQUENCY_50MHZ_30MHZ as a valid freq 2017-03-10 11:20:39 +01:00
.checkpatch.conf checkpatch.conf: Update rules 2017-03-09 04:37:28 +01:00
.clang-format
.gitignore .gitignore: ignore *.swo and option *.roms 2017-03-10 11:06:20 +01:00
.gitmodules Set up 3rdparty/libgfxinit 2016-10-29 01:35:03 +02:00
.gitreview
COPYING
MAINTAINERS MAINTAINERS: Update list 2017-03-08 04:33:30 +01:00
Makefile build system: mark sub-make invocations as parallelizable 2017-01-31 18:51:55 +01:00
Makefile.inc build system: mark sub-make invocations as parallelizable 2017-01-31 18:51:55 +01:00
README Remove extra newlines from the end of all coreboot files. 2016-07-31 18:19:33 +02:00
gnat.adc gnat.adc: Do not generate assertion code for Refined_Post 2016-10-29 01:33:31 +02:00
toolchain.inc Add minimal GNAT run time system (RTS) 2016-09-19 11:14:49 +02:00

README

-------------------------------------------------------------------------------
coreboot README
-------------------------------------------------------------------------------

coreboot is a Free Software project aimed at replacing the proprietary BIOS
(firmware) found in most computers.  coreboot performs a little bit of
hardware initialization and then executes additional boot logic, called a
payload.

With the separation of hardware initialization and later boot logic,
coreboot can scale from specialized applications that run directly
firmware, run operating systems in flash, load custom
bootloaders, or implement firmware standards, like PC BIOS services or
UEFI. This allows for systems to only include the features necessary
in the target application, reducing the amount of code and flash space
required.

coreboot was formerly known as LinuxBIOS.


Payloads
--------

After the basic initialization of the hardware has been performed, any
desired "payload" can be started by coreboot.

See http://www.coreboot.org/Payloads for a list of supported payloads.


Supported Hardware
------------------

coreboot supports a wide range of chipsets, devices, and mainboards.

For details please consult:

 * http://www.coreboot.org/Supported_Motherboards
 * http://www.coreboot.org/Supported_Chipsets_and_Devices


Build Requirements
------------------

 * make
 * gcc / g++
   Because Linux distribution compilers tend to use lots of patches. coreboot
   does lots of "unusual" things in its build system, some of which break due
   to those patches, sometimes by gcc aborting, sometimes - and that's worse -
   by generating broken object code.
   Two options: use our toolchain (eg. make crosstools-i386) or enable the
   ANY_TOOLCHAIN Kconfig option if you're feeling lucky (no support in this
   case).
 * iasl (for targets with ACPI support)

Optional:

 * doxygen (for generating/viewing documentation)
 * gdb (for better debugging facilities on some targets)
 * ncurses (for 'make menuconfig' and 'make nconfig')
 * flex and bison (for regenerating parsers)


Building coreboot
-----------------

Please consult http://www.coreboot.org/Build_HOWTO for details.


Testing coreboot Without Modifying Your Hardware
------------------------------------------------

If you want to test coreboot without any risks before you really decide
to use it on your hardware, you can use the QEMU system emulator to run
coreboot virtually in QEMU.

Please see http://www.coreboot.org/QEMU for details.


Website and Mailing List
------------------------

Further details on the project, a FAQ, many HOWTOs, news, development
guidelines and more can be found on the coreboot website:

  http://www.coreboot.org

You can contact us directly on the coreboot mailing list:

  http://www.coreboot.org/Mailinglist


Copyright and License
---------------------

The copyright on coreboot is owned by quite a large number of individual
developers and companies. Please check the individual source files for details.

coreboot is licensed under the terms of the GNU General Public License (GPL).
Some files are licensed under the "GPL (version 2, or any later version)",
and some files are licensed under the "GPL, version 2". For some parts, which
were derived from other projects, other (GPL-compatible) licenses may apply.
Please check the individual source files for details.

This makes the resulting coreboot images licensed under the GPL, version 2.