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rockchip/rk3399: calculate clocks based on parent clock speed 

Currently aclkm pclkdbg atclk clocks use apll_l as a parent, but the
apll_l frequency may change in firmware, so we need to caculate the div
value based on the apll_l frequency.

BRANCH=None
BUG=chrome-os-partner:54376
TEST=Boot from Gru

Change-Id: I2bd8886168453ce98efec58b5490c2430762769b
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: 116ae863a504630e2aff056564836d84198fcae2
Original-Change-Id: I7e3a5d9e3f608ddf15592d893117c92767fcd015
Original-Signed-off-by: Lin Huang <hl@rock-chips.com>
Original-Signed-off-by: Douglas Anderson <dianders@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/356397
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15581
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Lin Huang 2016-06-28 11:10:54 +08:00 committed by Martin Roth
parent 9e624fc27f
commit e3d78b82a7
2 changed files with 8 additions and 11 deletions
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18
src/soc/rockchip/rk3399/clock.c
View File

@ -31,12 +31,13 @@ struct pll_div {
u32 postdiv1;
u32 postdiv2;
u32 frac;
u32 freq;
};
#define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\
.refdiv = _refdiv,\
.fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
.postdiv1 = _postdiv1, .postdiv2 = _postdiv2};\
.postdiv1 = _postdiv1, .postdiv2 = _postdiv2, .freq = hz};\
_Static_assert(((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ) *\
OSC_HZ / (_refdiv * _postdiv1 * _postdiv2) == hz,\
#hz "Hz cannot be hit with PLL "\
@ -491,20 +492,17 @@ void rkclk_configure_cpu(enum apll_l_frequencies apll_l_freq)
u32 aclkm_div;
u32 pclk_dbg_div;
u32 atclk_div;
u32 apll_l_hz;
apll_l_hz = apll_l_cfgs[apll_l_freq]->freq;
rkclk_set_pll(&cru_ptr->apll_l_con[0], apll_l_cfgs[apll_l_freq]);
aclkm_div = APLL_HZ / ACLKM_CORE_HZ - 1;
assert((aclkm_div + 1) * ACLKM_CORE_HZ == APLL_HZ &&
aclkm_div < 0x1f);
aclkm_div = div_round_up(apll_l_hz, ACLKM_CORE_HZ) - 1;
pclk_dbg_div = APLL_HZ / PCLK_DBG_HZ - 1;
assert((pclk_dbg_div + 1) * PCLK_DBG_HZ == APLL_HZ &&
pclk_dbg_div < 0x1f);
pclk_dbg_div = div_round_up(apll_l_hz, PCLK_DBG_HZ) - 1;
atclk_div = APLL_HZ / ATCLK_CORE_HZ - 1;
assert((atclk_div + 1) * ATCLK_CORE_HZ == APLL_HZ &&
atclk_div < 0x1f);
atclk_div = div_round_up(apll_l_hz, ATCLK_CORE_HZ) - 1;
write32(&cru_ptr->clksel_con[0],
RK_CLRSETBITS(ACLKM_CORE_L_DIV_CON_MASK <<

1
src/soc/rockchip/rk3399/include/soc/clock.h
View File

@ -73,7 +73,6 @@ static struct rk3399_pmucru_reg * const pmucru_ptr = (void *)PMUCRU_BASE;
static struct rk3399_cru_reg * const cru_ptr = (void *)CRU_BASE;
#define OSC_HZ (24*MHz)
#define APLL_HZ (600*MHz)
#define GPLL_HZ (594*MHz)
#define CPLL_HZ (384*MHz)
#define PPLL_HZ (594*MHz)