baytrail: Enable GFX device
- Ungate display in PUNIT - Set GSM to 64MB since 32MB is not supported in <C0 stepping - Initialize power management registers in GTT - Execute VBIOS if found BUG=chrome-os-partner:23507 BRANCH=rambi TEST=build and boot to dev screen via HDMI on rambi Change-Id: Idb032c7ea7f16b651b4c921e3429a652fe663a5d Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/174922 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4907 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This commit is contained in:
Duncan Laurie
Aaron Durbin
parent
e549e94d03
commit
e3f75f8eca
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@ -18,6 +18,7 @@ romstage-$(CONFIG_CACHE_MRC_SETTINGS) += mrc_cache.c
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ramstage-y += spi.c
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ramstage-y += spi.c
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smm-y += spi.c
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smm-y += spi.c
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ramstage-y += chip.c
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ramstage-y += chip.c
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ramstage-y += gfx.c
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ramstage-y += iosf.c
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ramstage-y += iosf.c
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romstage-y += iosf.c
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romstage-y += iosf.c
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ramstage-y += northcluster.c
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ramstage-y += northcluster.c
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@ -155,5 +155,8 @@ void iosf_punit_write(int reg, uint32_t val);
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#define BIOS_RESET_CPL 0x05
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#define BIOS_RESET_CPL 0x05
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# define BIOS_RESET_CPL_ALL_DONE (1 << 1)
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# define BIOS_RESET_CPL_ALL_DONE (1 << 1)
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# define BIOS_RESET_CPL_RESET_DONE (1 << 0)
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# define BIOS_RESET_CPL_RESET_DONE (1 << 0)
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#define PUNIT_PWRGT_CONTROL 0x60
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#define PUNIT_PWRGT_STATUS 0x61
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#define PUNIT_GPU_EC_VIRUS 0xd2
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#endif /* _BAYTRAIL_IOSF_H_ */
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#endif /* _BAYTRAIL_IOSF_H_ */
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@ -0,0 +1,399 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2013 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <arch/io.h>
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#include <console/console.h>
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#include <delay.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <baytrail/gfx.h>
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#include <baytrail/iosf.h>
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#include <baytrail/pci_devs.h>
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#include <baytrail/ramstage.h>
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struct gt_reg {
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u32 reg;
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u32 andmask;
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u32 ormask;
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};
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static const struct gt_reg gfx_powermeter_weights[] = {
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/* SET1 */
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{ 0xA800, 0xFFFFFFFF, 0x00000000 },
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{ 0xA804, 0xFFFFFFFF, 0x00000000 },
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{ 0xA808, 0xFFFFFFFF, 0x0000ff0A },
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{ 0xA80C, 0xFFFFFFFF, 0x1D000000 },
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{ 0xA810, 0xFFFFFFFF, 0xAC004900 },
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{ 0xA814, 0xFFFFFFFF, 0x000F0000 },
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{ 0xA818, 0xFFFFFFFF, 0x5A000000 },
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{ 0xA81C, 0xFFFFFFFF, 0x2600001F },
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{ 0xA820, 0xFFFFFFFF, 0x00090000 },
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{ 0xA824, 0xFFFFFFFF, 0x2000ff00 },
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{ 0xA828, 0xFFFFFFFF, 0xff090016 },
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{ 0xA82C, 0xFFFFFFFF, 0x00000000 },
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{ 0xA830, 0xFFFFFFFF, 0x00000100 },
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{ 0xA834, 0xFFFFFFFF, 0x00A00F51 },
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{ 0xA838, 0xFFFFFFFF, 0x000B0000 },
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{ 0xA83C, 0xFFFFFFFF, 0xcb7D3307 },
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{ 0xA840, 0xFFFFFFFF, 0x003C0000 },
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{ 0xA844, 0xFFFFFFFF, 0xFFFF0000 },
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{ 0xA848, 0xFFFFFFFF, 0x00220000 },
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{ 0xA84c, 0xFFFFFFFF, 0x43000000 },
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{ 0xA850, 0xFFFFFFFF, 0x00000800 },
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{ 0xA854, 0xFFFFFFFF, 0x00000F00 },
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{ 0xA858, 0xFFFFFFFF, 0x00000021 },
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{ 0xA85c, 0xFFFFFFFF, 0x00000000 },
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{ 0xA860, 0xFFFFFFFF, 0x00190000 },
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{ 0xAA80, 0xFFFFFFFF, 0x00FF00FF },
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{ 0xAA84, 0xFFFFFFFF, 0x00000000 },
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{ 0x1300A4, 0xFFFFFFFF, 0x00000000 },
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/* SET2 */
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{ 0xA900, 0xFFFFFFFF, 0x00000000 },
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{ 0xA904, 0xFFFFFFFF, 0x00000000 },
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{ 0xA908, 0xFFFFFFFF, 0x00000000 },
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{ 0xa90c, 0xFFFFFFFF, 0x1D000000 },
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{ 0xa910, 0xFFFFFFFF, 0xAC005000 },
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{ 0xa914, 0xFFFFFFFF, 0x000F0000 },
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{ 0xa918, 0xFFFFFFFF, 0x5A000000 },
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{ 0xa91c, 0xFFFFFFFF, 0x2600001F },
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{ 0xa920, 0xFFFFFFFF, 0x00090000 },
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{ 0xa924, 0xFFFFFFFF, 0x2000ff00 },
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{ 0xa928, 0xFFFFFFFF, 0xff090016 },
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{ 0xa92c, 0xFFFFFFFF, 0x00000000 },
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{ 0xa930, 0xFFFFFFFF, 0x00000100 },
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{ 0xa934, 0xFFFFFFFF, 0x00A00F51 },
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{ 0xa938, 0xFFFFFFFF, 0x000B0000 },
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{ 0xA93C, 0xFFFFFFFF, 0xcb7D3307 },
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{ 0xA940, 0xFFFFFFFF, 0x003C0000 },
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{ 0xA944, 0xFFFFFFFF, 0xFFFF0000 },
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{ 0xA948, 0xFFFFFFFF, 0x00220000 },
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{ 0xA94C, 0xFFFFFFFF, 0x43000000 },
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{ 0xA950, 0xFFFFFFFF, 0x00000800 },
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{ 0xA954, 0xFFFFFFFF, 0x00000000 },
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{ 0xA960, 0xFFFFFFFF, 0x00000000 },
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/* SET3 */
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{ 0xaa3c, 0xFFFFFFFF, 0x00000000 },
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{ 0xaa54, 0xFFFFFFFF, 0x00000000 },
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{ 0xaa60, 0xFFFFFFFF, 0x00000000 },
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/* Enable PowerMeter Counters */
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{ 0xA248, 0xFFFFFFFF, 0x00000058 },
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{ 0 }
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};
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static const struct gt_reg gfx_rc6_registers[] = {
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{ 0xA090, 0xFFFFFFFF, 0x00000000 },
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/* RC1e - RC6/6p - RC6pp Wake Rate Limits */
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{ 0xA09C, 0xFFFFFFFF, 0x00280000 },
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{ 0xA0A8, 0xFFFFFFFF, 0x0001E848 },
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{ 0xA0AC, 0xFFFFFFFF, 0x00000019 },
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/* RC Sleep / RCx Thresholds */
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{ 0xA0B0, 0xFFFFFFFF, 0x00000000 },
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{ 0xA0B8, 0xFFFFFFFF, 0x00000557 },
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{ 0 }
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};
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static const struct gt_reg gfx_turbo_registers[] = {
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/* Render/Video/Blitter Idle Max Count */
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{ 0x2054, 0xFFFFFFFF, 0x0000000A },
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{ 0x12054, 0xFFFFFFFF, 0x0000000A },
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{ 0x22054, 0xFFFFFFFF, 0x0000000A },
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/* RP Down Timeout */
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{ 0xA010, 0xFFFFFFFF, 0x000F4240 },
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{ 0 }
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};
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static const struct gt_reg gfx_turbo_ctl_registers[] = {
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/* RP Up/Down Threshold */
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{ 0xA02C, 0xFFFFFFFF, 0x0000E8E8 },
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{ 0xA030, 0xFFFFFFFF, 0x0003BD08 },
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/* RP Up/Down EI */
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{ 0xA068, 0xFFFFFFFF, 0x000101D0 },
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{ 0xA06C, 0xFFFFFFFF, 0x00055730 },
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{ 0 }
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};
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static struct resource *gtt_res = NULL;
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static inline unsigned long gtt_read(unsigned long reg)
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{
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u32 val;
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val = read32(gtt_res->base + reg);
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return val;
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}
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static inline void gtt_write(unsigned long reg, unsigned long data)
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{
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write32(gtt_res->base + reg, data);
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}
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static inline void gtt_rmw(u32 reg, u32 andmask, u32 ormask)
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{
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u32 val = gtt_read(reg);
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val &= andmask;
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val |= ormask;
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gtt_write(reg, val);
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}
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static void gtt_write_regs(const struct gt_reg *gt)
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{
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for (; gt && gt->reg; gt++)
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gtt_rmw(gt->reg, gt->andmask, gt->ormask);
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}
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#define GFX_POLL_RETRY 10000
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static int gtt_poll(u32 reg, u32 mask, u32 value)
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{
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unsigned try = GFX_POLL_RETRY;
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u32 data;
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while (try--) {
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data = gtt_read(reg);
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if ((data & mask) == value)
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return 1;
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udelay(100);
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}
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printk(BIOS_ERR, "GTT timeout\n");
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return 0;
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}
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static int gfx_poll_power_gate(u32 mask, u32 value)
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{
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unsigned try = GFX_POLL_RETRY;
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u32 data;
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while (try--) {
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data = iosf_punit_read(PUNIT_PWRGT_STATUS);
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if ((data & mask) == value)
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return 1;
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udelay(100);
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}
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printk(BIOS_ERR, "Power Gate timeout\n");
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return 0;
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}
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/*
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* Lock Power Context Base Register to point to a 24KB block
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* of memory in GSM. Power context save data is stored here.
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*/
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static void gfx_lock_pcbase(device_t dev)
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{
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const u16 gms_size_map[17] = { 0,32,64,96,128,160,192,224,256,
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288,320,352,384,416,448,480,512 };
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u32 pcsize = 24 << 10; /* 24KB */
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u32 wopcmsz = 0x100000; /* PAVP offset */
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u32 gms, gmsize, pcbase;
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gms = pci_read_config32(dev, GGC) & GGC_GSM_SIZE_MASK;
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gms >>= 3;
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if (gms > sizeof(gms_size_map))
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return;
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gmsize = gms_size_map[gms];
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/* PcBase = BDSM + GMS Size - WOPCMSZ - PowerContextSize */
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pcbase = pci_read_config32(dev, GSM_BASE) & 0xfff00000;
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pcbase += (gmsize-1) * wopcmsz - pcsize;
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pcbase |= 1; /* Lock */
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gtt_write(0x182120, pcbase);
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}
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static void gfx_pm_init(device_t dev)
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{
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printk(BIOS_INFO, "GFX: Power Management Init\n");
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/*
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* Allow-Wake render/media wells.
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* Used by PUNIT as part of S0IX save/restore.
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*/
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gtt_rmw(0x130090, ~1, 1);
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if (!gtt_poll(0x130094, 1, 1)) {
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printk(BIOS_ERR, "gfx_pm_init: Unable to allow-wake\n");
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return;
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}
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/* Render Force-Wake */
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gtt_write(0x1300B0, 0x80008000);
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if (!gtt_poll(0x1300B4, 0x8000, 0x8000)) {
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printk(BIOS_ERR, "gfx_pm_init: Unable to force-wake render\n");
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return;
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}
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/* Media Force-Wake */
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gtt_write(0x1300B8, 0x80008000);
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if (!gtt_poll(0x1300BC, 0x8000, 0x8000)) {
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printk(BIOS_ERR, "gfx_pm_init: Unable to force-wake media\n");
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return;
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};
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/* Workaround - X0:261954/A0:261955 */
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gtt_rmw(0x182060, ~0xf, 1);
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/* Program GT PowerMeter weights */
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gtt_write_regs(gfx_powermeter_weights);
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/* Program PUNIT_GPU_EC_VIRUS based on DPTF SDP */
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/* SDP Profile 4 == 0x11940, others 0xcf08 */
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iosf_punit_write(PUNIT_GPU_EC_VIRUS, 0xcf08);
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/* GfxPause */
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gtt_write(0xa000, 0x00071388);
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/* Dynamic EU Control Settings */
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gtt_write(0xa080, 0x00000004);
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/* Lock ECO Bit Settings */
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gtt_write(0xa180, 0x80000000);
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/* DOP Clock Gating */
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gtt_write(0x9424, 0x00000001);
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/* MBCunit will send the VCR (Fuse) writes as NP-W */
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gtt_rmw(0x907c, 0xfffeffff, 0x00010000);
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/* RC6 Settings */
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gtt_write_regs(gfx_rc6_registers);
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/* Turbo Settings */
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gtt_write_regs(gfx_turbo_registers);
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/* Turbo Control Settings */
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gtt_write_regs(gfx_turbo_ctl_registers);
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/* RP Idle Hysteresis */
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gtt_write(0xa070, 0x0000000a);
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/* HW RC6 Control Settings */
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gtt_write(0xa090, 0x11000000);
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/* RP Control */
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gtt_write(0xa024, 0x00000592);
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/* Enable PM Interrupts */
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gtt_write(0x44024, 0x03000000);
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gtt_write(0x4402c, 0x03000076);
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gtt_write(0xa168, 0x0000007e);
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/* Lock power context base */
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gfx_lock_pcbase(dev);
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/* Aggressive Clock Gating */
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gtt_write(0x9400, 0);
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gtt_write(0x9404, 0);
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gtt_write(0x9408, 0);
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gtt_write(0x940c, 0);
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}
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static void gfx_pre_vbios_init(device_t dev)
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{
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/* Display */
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iosf_punit_write(PUNIT_PWRGT_CONTROL, 0xc0);
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gfx_poll_power_gate(0xc0, 0xc0);
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/* Tx/Rx Lanes */
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iosf_punit_write(PUNIT_PWRGT_CONTROL, 0xfff0c0);
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gfx_poll_power_gate(0xfff0c0, 0xfff0c0);
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/* Common Lane */
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iosf_punit_write(PUNIT_PWRGT_CONTROL, 0xfffcc0);
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||||||
|
gfx_poll_power_gate(0xfffcc0, 0xfffcc0);
|
||||||
|
|
||||||
|
/* Ungating Tx only */
|
||||||
|
iosf_punit_write(PUNIT_PWRGT_CONTROL, 0xf00cc0);
|
||||||
|
gfx_poll_power_gate(0xfffcc0, 0xf00cc0);
|
||||||
|
|
||||||
|
/* Ungating Common Lane only */
|
||||||
|
iosf_punit_write(PUNIT_PWRGT_CONTROL, 0xf000c0);
|
||||||
|
gfx_poll_power_gate(0xffffc0, 0xf000c0);
|
||||||
|
|
||||||
|
/* Ungating Display */
|
||||||
|
iosf_punit_write(PUNIT_PWRGT_CONTROL, 0xf00000);
|
||||||
|
gfx_poll_power_gate(0xfffff0, 0xf00000);
|
||||||
|
}
|
||||||
|
|
||||||
|
static void gfx_post_vbios_init(device_t dev)
|
||||||
|
{
|
||||||
|
/* Deassert Render Force-Wake */
|
||||||
|
gtt_write(0x1300B0, 0x80000000);
|
||||||
|
gtt_poll(0x1300B4, 0x8000, 0);
|
||||||
|
|
||||||
|
/* Deassert Media Force-Wake */
|
||||||
|
gtt_write(0x1300B8, 0x80000000);
|
||||||
|
gtt_poll(0x1300BC, 0x8000, 0);
|
||||||
|
|
||||||
|
/* Set Lock bits */
|
||||||
|
pci_write_config32(dev, GGC, pci_read_config32(dev, GGC) | 1);
|
||||||
|
pci_write_config32(dev, GSM_BASE, pci_read_config32(dev, GSM_BASE) | 1);
|
||||||
|
pci_write_config32(dev, GTT_BASE, pci_read_config32(dev, GTT_BASE) | 1);
|
||||||
|
}
|
||||||
|
|
||||||
|
static void gfx_init(device_t dev)
|
||||||
|
{
|
||||||
|
u32 reg32;
|
||||||
|
|
||||||
|
/* Find GTT resource */
|
||||||
|
gtt_res = find_resource(dev, PCI_BASE_ADDRESS_0);
|
||||||
|
if (!gtt_res || !gtt_res->base)
|
||||||
|
return;
|
||||||
|
|
||||||
|
/* GFX needs to be Bus Master */
|
||||||
|
reg32 = pci_read_config32(dev, PCI_COMMAND);
|
||||||
|
reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
|
||||||
|
pci_write_config32(dev, PCI_COMMAND, reg32);
|
||||||
|
|
||||||
|
/* Pre VBIOS Init */
|
||||||
|
gfx_pre_vbios_init(dev);
|
||||||
|
gfx_pm_init(dev);
|
||||||
|
|
||||||
|
/* Run VBIOS */
|
||||||
|
pci_dev_init(dev);
|
||||||
|
|
||||||
|
/* Post VBIOS Init */
|
||||||
|
gfx_post_vbios_init(dev);
|
||||||
|
}
|
||||||
|
|
||||||
|
static struct device_operations gfx_device_ops = {
|
||||||
|
.read_resources = pci_dev_read_resources,
|
||||||
|
.set_resources = pci_dev_set_resources,
|
||||||
|
.enable_resources = pci_dev_enable_resources,
|
||||||
|
.init = gfx_init,
|
||||||
|
.ops_pci = &soc_pci_ops,
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct pci_driver gfx_driver __pci_driver = {
|
||||||
|
.ops = &gfx_device_ops,
|
||||||
|
.vendor = PCI_VENDOR_ID_INTEL,
|
||||||
|
.device = GFX_DEVID,
|
||||||
|
};
|
||||||
|
|
@ -37,7 +37,8 @@ void gfx_init(void)
|
||||||
msac = pci_read_config8(gfx_dev, MSAC);
|
msac = pci_read_config8(gfx_dev, MSAC);
|
||||||
|
|
||||||
ggc &= ~(GGC_GTT_SIZE_MASK | GGC_GSM_SIZE_MASK);
|
ggc &= ~(GGC_GTT_SIZE_MASK | GGC_GSM_SIZE_MASK);
|
||||||
ggc |= GGC_GTT_SIZE_2MB | GGC_GSM_SIZE_32MB;
|
/* 32MB GSM is not supported with <C0 stepping. */
|
||||||
|
ggc |= GGC_GTT_SIZE_2MB | GGC_GSM_SIZE_64MB;
|
||||||
/* Enable VGA decoding as well. */
|
/* Enable VGA decoding as well. */
|
||||||
ggc &= ~(GGC_VGA_DISABLE);
|
ggc &= ~(GGC_VGA_DISABLE);
|
||||||
|
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue