mb/intel/adlrvp_n: Add initial code for adl-n variant board
This patch adds the following list of changes: 1. Create a new devicetree for adlrvp-n and copy contents of adlrvp-p devictree. 2. Add support for 2 mainboards as ADL-N board with default EC (Windows SKU) and Chrome EC (Chrome SKU) and copy overridetree contents from adlrvp-p. 3. Add mainboard Kconfig to Kconfig.name file 4. Handle mainboard names in Kconfig file for ADLRVP N 5. Add config options to pick the adlrvp_n devicetree Change-Id: I4abf3bf62ec0398ae75e21575a2fab0d44b5c7ad Signed-off-by: Usha P <usha.p@intel.com> Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59915 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Krishna Prasad Bhat
Felix Held
parent
fc373c7dac
commit
e3fd52a802
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@ -58,6 +58,18 @@ config BOARD_INTEL_ADLRVP_M_EXT_EC
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select SOC_INTEL_ALDERLAKE_PCH_M
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select SOC_INTEL_ALDERLAKE_PCH_M
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select SPI_TPM
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select SPI_TPM
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config BOARD_INTEL_ADLRVP_N
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select BOARD_INTEL_ADLRVP_COMMON
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select DRIVERS_UART_8250IO
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select MAINBOARD_USES_IFD_EC_REGION
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select SOC_INTEL_ALDERLAKE_PCH_N
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config BOARD_INTEL_ADLRVP_N_EXT_EC
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select BOARD_INTEL_ADLRVP_COMMON
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select DRIVERS_INTEL_PMC
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select INTEL_LPSS_UART_FOR_CONSOLE
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select SOC_INTEL_ALDERLAKE_PCH_N
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if BOARD_INTEL_ADLRVP_COMMON
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if BOARD_INTEL_ADLRVP_COMMON
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config CHROMEOS
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config CHROMEOS
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@ -77,11 +89,14 @@ config VARIANT_DIR
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default "adlrvp_p_mchp" if BOARD_INTEL_ADLRVP_P_MCHP
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default "adlrvp_p_mchp" if BOARD_INTEL_ADLRVP_P_MCHP
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default "adlrvp_m" if BOARD_INTEL_ADLRVP_M
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default "adlrvp_m" if BOARD_INTEL_ADLRVP_M
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default "adlrvp_m_ext_ec" if BOARD_INTEL_ADLRVP_M_EXT_EC
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default "adlrvp_m_ext_ec" if BOARD_INTEL_ADLRVP_M_EXT_EC
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default "adlrvp_n" if BOARD_INTEL_ADLRVP_N
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default "adlrvp_n_ext_ec" if BOARD_INTEL_ADLRVP_N_EXT_EC
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config GBB_HWID
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config GBB_HWID
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string
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string
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depends on CHROMEOS
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depends on CHROMEOS
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default "ADLRVPM" if BOARD_INTEL_ADLRVP_M || BOARD_INTEL_ADLRVP_M_EXT_EC
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default "ADLRVPM" if BOARD_INTEL_ADLRVP_M || BOARD_INTEL_ADLRVP_M_EXT_EC
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default "ADLRVPN" if BOARD_INTEL_ADLRVP_N || BOARD_INTEL_ADLRVP_N_EXT_EC
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default "ADLRVPP"
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default "ADLRVPP"
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config MAINBOARD_PART_NUMBER
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config MAINBOARD_PART_NUMBER
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@ -97,6 +112,7 @@ config MAINBOARD_FAMILY
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config DEVICETREE
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config DEVICETREE
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default "devicetree_m.cb" if BOARD_INTEL_ADLRVP_M || BOARD_INTEL_ADLRVP_M_EXT_EC
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default "devicetree_m.cb" if BOARD_INTEL_ADLRVP_M || BOARD_INTEL_ADLRVP_M_EXT_EC
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default "devicetree_n.cb" if BOARD_INTEL_ADLRVP_N || BOARD_INTEL_ADLRVP_N_EXT_EC
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default "devicetree.cb"
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default "devicetree.cb"
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config OVERRIDE_DEVICETREE
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config OVERRIDE_DEVICETREE
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@ -107,8 +123,8 @@ config DIMM_SPD_SIZE
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choice
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choice
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prompt "ON BOARD EC"
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prompt "ON BOARD EC"
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default ADL_INTEL_EC if BOARD_INTEL_ADLRVP_P || BOARD_INTEL_ADLRVP_M
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default ADL_INTEL_EC if BOARD_INTEL_ADLRVP_P || BOARD_INTEL_ADLRVP_M || BOARD_INTEL_ADLRVP_N
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default ADL_CHROME_EC if BOARD_INTEL_ADLRVP_P_EXT_EC || BOARD_INTEL_ADLRVP_M_EXT_EC || BOARD_INTEL_ADLRVP_P_MCHP
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default ADL_CHROME_EC if BOARD_INTEL_ADLRVP_P_EXT_EC || BOARD_INTEL_ADLRVP_M_EXT_EC || BOARD_INTEL_ADLRVP_P_MCHP || BOARD_INTEL_ADLRVP_N_EXT_EC
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help
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help
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This option allows you to select the on board EC to use.
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This option allows you to select the on board EC to use.
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Select whether the board has Intel EC or Chrome EC
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Select whether the board has Intel EC or Chrome EC
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@ -12,3 +12,9 @@ config BOARD_INTEL_ADLRVP_M
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config BOARD_INTEL_ADLRVP_M_EXT_EC
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config BOARD_INTEL_ADLRVP_M_EXT_EC
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bool "Alderlake-M RVP with Chrome EC"
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bool "Alderlake-M RVP with Chrome EC"
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config BOARD_INTEL_ADLRVP_N
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bool "Alderlake-N RVP"
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config BOARD_INTEL_ADLRVP_N_EXT_EC
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bool "Alderlake-N RVP with Chrome EC"
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@ -0,0 +1,427 @@
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chip soc/intel/alderlake
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# GPE configuration
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# Note that GPE events called out in ASL code rely on this
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# route. i.e. If this route changes then the affected GPE
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# offset bits also need to be changed.
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register "pmc_gpe0_dw0" = "GPP_B"
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register "pmc_gpe0_dw1" = "GPP_D"
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register "pmc_gpe0_dw2" = "GPP_E"
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# Enable HECI1 interface
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register "HeciEnabled" = "1"
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# FSP configuration
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# Enable CNVi BT
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register "CnviBtCore" = "true"
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# Sagv Configuration
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register "SaGv" = "SaGv_Enabled"
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register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" # Type-C Port1
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register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" # Type-C Port2
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register "usb2_ports[2]" = "USB2_PORT_MID(OC3)" # Type-C Port3
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register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WWAN
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register "usb2_ports[4]" = "USB2_PORT_MID(OC3)" # Type-C Port4
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register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # FPS connector
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register "usb2_ports[6]" = "USB2_PORT_MID(OC0)" # USB3/2 Type A port1
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register "usb2_ports[7]" = "USB2_PORT_MID(OC0)" # USB3/2 Type A port2
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register "usb2_ports[8]" = "USB2_PORT_MID(OC3)" # USB3/2 Type A port3
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register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WLAN
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register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC3)" # USB3/2 Type A port1
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register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A port2
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register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A port3
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register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 WWAN
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# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
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register "gen1_dec" = "0x00fc0801"
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register "gen2_dec" = "0x000c0201"
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# EC memory map range is 0x900-0x9ff
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register "gen3_dec" = "0x00fc0901"
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# Enable PCH PCIE RP 5 using CLK 2
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register "pch_pcie_rp[PCH_RP(5)]" = "{
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.clk_src = 2,
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.clk_req = 2,
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.flags = PCIE_RP_CLK_REQ_DETECT,
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}"
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# Enable PCH PCIE RP 6 using CLK 5
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register "pch_pcie_rp[PCH_RP(6)]" = "{
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.clk_src = 5,
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.clk_req = 5,
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.flags = PCIE_RP_CLK_REQ_DETECT,
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}"
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# Enable PCH PCIE RP 8 using free running CLK (0x80)
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# Clock source is shared with LAN and hence marked as free running.
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register "pch_pcie_rp[PCH_RP(8)]" = "{
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.flags = PCIE_RP_CLK_SRC_UNUSED,
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}"
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# Enable PCH PCIE RP 9 using CLK 1
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register "pch_pcie_rp[PCH_RP(9)]" = "{
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.clk_src = 1,
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.clk_req = 1,
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.flags = PCIE_RP_CLK_REQ_DETECT,
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}"
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# Enable PCH PCIE RP 11 for optane
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register "pch_pcie_rp[PCH_RP(11)]" = "{
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.flags = PCIE_RP_CLK_SRC_UNUSED,
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}"
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# Hybrid storage mode
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register "HybridStorageMode" = "1"
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register "SataSalpSupport" = "1"
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register "SataPortsEnable" = "{
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[0] = 1,
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[1] = 1,
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[2] = 1,
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[3] = 1,
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}"
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register "SataPortsDevSlp" = "{
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[0] = 1,
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[1] = 1,
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[2] = 1,
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[3] = 1,
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}"
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# Enable EDP in PortA
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register "DdiPortAConfig" = "1"
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# Enable HDMI in Port B
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register "ddi_ports_config" = "{
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[DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
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}"
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# TCSS USB3
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register "TcssAuxOri" = "0"
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register "s0ix_enable" = "1"
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register "dptf_enable" = "1"
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register "SerialIoI2cMode" = "{
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[PchSerialIoIndexI2C0] = PchSerialIoPci,
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[PchSerialIoIndexI2C1] = PchSerialIoPci,
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[PchSerialIoIndexI2C2] = PchSerialIoPci,
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[PchSerialIoIndexI2C3] = PchSerialIoPci,
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[PchSerialIoIndexI2C4] = PchSerialIoDisabled,
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[PchSerialIoIndexI2C5] = PchSerialIoPci,
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}"
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register "SerialIoGSpiMode" = "{
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[PchSerialIoIndexGSPI0] = PchSerialIoPci,
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[PchSerialIoIndexGSPI1] = PchSerialIoDisabled,
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[PchSerialIoIndexGSPI2] = PchSerialIoDisabled,
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[PchSerialIoIndexGSPI3] = PchSerialIoDisabled,
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}"
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register "SerialIoGSpiCsMode" = "{
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[PchSerialIoIndexGSPI0] = 0,
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[PchSerialIoIndexGSPI1] = 0,
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[PchSerialIoIndexGSPI2] = 0,
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[PchSerialIoIndexGSPI3] = 0,
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}"
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register "SerialIoGSpiCsState" = "{
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[PchSerialIoIndexGSPI0] = 0,
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[PchSerialIoIndexGSPI1] = 0,
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[PchSerialIoIndexGSPI2] = 0,
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[PchSerialIoIndexGSPI3] = 0,
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}"
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register "SerialIoUartMode" = "{
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[PchSerialIoIndexUART0] = PchSerialIoSkipInit,
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[PchSerialIoIndexUART1] = PchSerialIoDisabled,
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[PchSerialIoIndexUART2] = PchSerialIoDisabled,
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}"
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# HD Audio
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register "PchHdaDspEnable" = "1"
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register "PchHdaIDispLinkTmode" = "HDA_TMODE_8T"
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register "PchHdaIDispLinkFrequency" = "HDA_LINKFREQ_96MHZ"
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register "PchHdaIDispCodecEnable" = "1"
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register "CnviBtAudioOffload" = "true"
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# Intel Common SoC Config
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register "common_soc_config" = "{
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.i2c[0] = {
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.speed = I2C_SPEED_FAST,
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},
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.i2c[1] = {
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.speed = I2C_SPEED_FAST,
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},
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.i2c[2] = {
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.speed = I2C_SPEED_FAST,
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},
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.i2c[3] = {
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.speed = I2C_SPEED_FAST,
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},
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.i2c[5] = {
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.speed = I2C_SPEED_FAST,
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},
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}"
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device domain 0 on
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device ref pcie5 on end
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device ref igpu on end
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device ref dtt on
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chip drivers/intel/dptf
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## sensor information
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register "options.tsr[0].desc" = ""Ambient""
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register "options.tsr[1].desc" = ""Battery""
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register "options.tsr[2].desc" = ""DDR""
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register "options.tsr[3].desc" = ""Skin""
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## Active Policy
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# TODO: below values are initial reference values only
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register "policies.active" = "{
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[0] = {
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.target = DPTF_CPU,
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.thresholds = {
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TEMP_PCT(95, 90),
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TEMP_PCT(90, 80),
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}
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},
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[1] = {
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.target = DPTF_TEMP_SENSOR_0,
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.thresholds = {
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TEMP_PCT(80, 90),
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TEMP_PCT(70, 80),
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}
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}
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}"
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## Passive Policy
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# TODO: below values are initial reference values only
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register "policies.passive" = "{
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[0] = DPTF_PASSIVE(CPU, CPU, 95, 10000),
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[1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 85, 50000),
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[2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_1, 85, 50000),
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[3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 85, 50000),
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[4] = DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 85, 50000),
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}"
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## Critical Policy
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# TODO: below values are initial reference values only
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register "policies.critical" = "{
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[0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN),
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[1] = DPTF_CRITICAL(TEMP_SENSOR_0, 95, SHUTDOWN),
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[2] = DPTF_CRITICAL(TEMP_SENSOR_1, 95, SHUTDOWN),
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[3] = DPTF_CRITICAL(TEMP_SENSOR_2, 95, SHUTDOWN),
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[4] = DPTF_CRITICAL(TEMP_SENSOR_3, 95, SHUTDOWN),
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}"
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## Power Limits Control
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register "controls.power_limits" = "{
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.pl1 = {
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.min_power = 35000,
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.max_power = 45000,
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.time_window_min = 28 * MSECS_PER_SEC,
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.time_window_max = 32 * MSECS_PER_SEC,
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.granularity = 200,
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},
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.pl2 = {
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.min_power = 56000,
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.max_power = 56000,
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.time_window_min = 28 * MSECS_PER_SEC,
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.time_window_max = 32 * MSECS_PER_SEC,
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.granularity = 1000,
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}
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}"
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## Charger Performance Control (Control, mA)
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register "controls.charger_perf" = "{
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[0] = { 255, 3000 },
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[1] = { 24, 1500 },
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[2] = { 16, 1000 },
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[3] = { 8, 500 }
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}"
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## Fan Performance Control (Percent, Speed, Noise, Power)
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register "controls.fan_perf" = "{
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[0] = { 90, 6700, 220, 2200, },
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||||||
|
[1] = { 80, 5800, 180, 1800, },
|
||||||
|
[2] = { 70, 5000, 145, 1450, },
|
||||||
|
[3] = { 60, 4900, 115, 1150, },
|
||||||
|
[4] = { 50, 3838, 90, 900, },
|
||||||
|
[5] = { 40, 2904, 55, 550, },
|
||||||
|
[6] = { 30, 2337, 30, 300, },
|
||||||
|
[7] = { 20, 1608, 15, 150, },
|
||||||
|
[8] = { 10, 800, 10, 100, },
|
||||||
|
[9] = { 0, 0, 0, 50, }
|
||||||
|
}"
|
||||||
|
|
||||||
|
## Fan options
|
||||||
|
register "options.fan.fine_grained_control" = "1"
|
||||||
|
register "options.fan.step_size" = "2"
|
||||||
|
|
||||||
|
device generic 0 alias dptf_policy on end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
device ref ipu on
|
||||||
|
chip drivers/intel/mipi_camera
|
||||||
|
register "acpi_uid" = "0x50000"
|
||||||
|
register "acpi_name" = ""IPU0""
|
||||||
|
register "device_type" = "INTEL_ACPI_CAMERA_CIO2"
|
||||||
|
|
||||||
|
register "cio2_num_ports" = "2"
|
||||||
|
register "cio2_lanes_used" = "{2,2}"
|
||||||
|
register "cio2_lane_endpoint[0]" = ""^I2C5.CAM1""
|
||||||
|
register "cio2_lane_endpoint[1]" = ""^I2C1.CAM0""
|
||||||
|
register "cio2_prt[0]" = "2"
|
||||||
|
register "cio2_prt[1]" = "1"
|
||||||
|
device generic 0 on end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
device ref pcie4_0 on end
|
||||||
|
device ref pcie4_1 on end
|
||||||
|
device ref tbt_pcie_rp0 on end
|
||||||
|
device ref tbt_pcie_rp1 on end
|
||||||
|
device ref tbt_pcie_rp2 on end
|
||||||
|
device ref tbt_pcie_rp3 on end
|
||||||
|
device ref crashlog off end
|
||||||
|
device ref tcss_xhci on end
|
||||||
|
device ref tcss_dma0 on end
|
||||||
|
device ref tcss_dma1 on end
|
||||||
|
device ref xhci on
|
||||||
|
chip drivers/usb/acpi
|
||||||
|
register "desc" = ""Root Hub""
|
||||||
|
register "type" = "UPC_TYPE_HUB"
|
||||||
|
device ref xhci_root_hub on
|
||||||
|
chip drivers/usb/acpi
|
||||||
|
register "desc" = ""Bluetooth""
|
||||||
|
register "type" = "UPC_TYPE_INTERNAL"
|
||||||
|
device ref usb2_port10 on end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
device ref cnvi_wifi on
|
||||||
|
chip drivers/wifi/generic
|
||||||
|
register "wake" = "GPE0_PME_B0"
|
||||||
|
device generic 0 on end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
device ref i2c0 on end
|
||||||
|
device ref i2c1 on
|
||||||
|
chip drivers/intel/mipi_camera
|
||||||
|
register "acpi_hid" = ""OVTI5675""
|
||||||
|
register "acpi_uid" = "0"
|
||||||
|
register "acpi_name" = ""CAM0""
|
||||||
|
register "chip_name" = ""Ov 5675 Camera""
|
||||||
|
register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
|
||||||
|
|
||||||
|
register "ssdb.lanes_used" = "2"
|
||||||
|
register "ssdb.vcm_type" = "0x0C"
|
||||||
|
register "vcm_name" = ""VCM0""
|
||||||
|
register "num_freq_entries" = "1"
|
||||||
|
register "link_freq[0]" = "450000000"
|
||||||
|
register "remote_name" = ""IPU0""
|
||||||
|
|
||||||
|
register "has_power_resource" = "1"
|
||||||
|
#Controls
|
||||||
|
register "clk_panel.clks[0].clknum" = "0" #IMGCLKOUT_0
|
||||||
|
register "clk_panel.clks[0].freq" = "1" #19.2 Mhz
|
||||||
|
register "gpio_panel.gpio[0].gpio_num" = "GPP_B23" #power_enable
|
||||||
|
register "gpio_panel.gpio[1].gpio_num" = "GPP_R5" #reset
|
||||||
|
|
||||||
|
#_ON
|
||||||
|
register "on_seq.ops_cnt" = "4"
|
||||||
|
register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)"
|
||||||
|
register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 2)"
|
||||||
|
register "on_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 1)"
|
||||||
|
register "on_seq.ops[3]" = "SEQ_OPS_GPIO_ENABLE(1, 1)"
|
||||||
|
|
||||||
|
#_OFF
|
||||||
|
register "off_seq.ops_cnt" = "3"
|
||||||
|
register "off_seq.ops[0]" = "SEQ_OPS_CLK_DISABLE(0, 0)"
|
||||||
|
register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(1, 0)"
|
||||||
|
register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(0, 0)"
|
||||||
|
|
||||||
|
device i2c 36 on end
|
||||||
|
end
|
||||||
|
chip drivers/intel/mipi_camera
|
||||||
|
register "acpi_uid" = "3"
|
||||||
|
register "acpi_name" = ""VCM0""
|
||||||
|
register "chip_name" = ""DW AF VCM""
|
||||||
|
register "device_type" = "INTEL_ACPI_CAMERA_VCM"
|
||||||
|
|
||||||
|
register "pr0" = ""\\_SB.PCI0.I2C1.CAM0.PRIC""
|
||||||
|
register "vcm_compat" = ""dongwoon,dw9714""
|
||||||
|
|
||||||
|
device i2c 0C on end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
device ref i2c2 on end
|
||||||
|
device ref i2c3 on end
|
||||||
|
device ref heci1 on end
|
||||||
|
device ref sata on end
|
||||||
|
device ref i2c5 on
|
||||||
|
chip drivers/intel/mipi_camera
|
||||||
|
register "acpi_hid" = ""OVTI5675""
|
||||||
|
register "acpi_uid" = "0"
|
||||||
|
register "acpi_name" = ""CAM1""
|
||||||
|
register "chip_name" = ""Ov 5675 Camera""
|
||||||
|
register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
|
||||||
|
|
||||||
|
register "ssdb.lanes_used" = "2"
|
||||||
|
register "num_freq_entries" = "1"
|
||||||
|
register "link_freq[0]" = "450000000"
|
||||||
|
register "remote_name" = ""IPU0""
|
||||||
|
|
||||||
|
register "has_power_resource" = "1"
|
||||||
|
#Controls
|
||||||
|
register "clk_panel.clks[0].clknum" = "1" #IMGCLKOUT_1
|
||||||
|
register "clk_panel.clks[0].freq" = "1" #19.2 Mhz
|
||||||
|
register "gpio_panel.gpio[0].gpio_num" = "GPP_E16" #power_enable
|
||||||
|
register "gpio_panel.gpio[1].gpio_num" = "GPP_E15" #reset
|
||||||
|
|
||||||
|
#_ON
|
||||||
|
register "on_seq.ops_cnt" = "4"
|
||||||
|
register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)"
|
||||||
|
register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 2)"
|
||||||
|
register "on_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 1)"
|
||||||
|
register "on_seq.ops[3]" = "SEQ_OPS_GPIO_ENABLE(1, 1)"
|
||||||
|
|
||||||
|
#_OFF
|
||||||
|
register "off_seq.ops_cnt" = "3"
|
||||||
|
register "off_seq.ops[0]" = "SEQ_OPS_CLK_DISABLE(0, 0)"
|
||||||
|
register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(1, 0)"
|
||||||
|
register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(0, 0)"
|
||||||
|
|
||||||
|
device i2c 36 on end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
device ref pcie_rp1 on end
|
||||||
|
device ref pcie_rp3 on end # W/A to FSP issue
|
||||||
|
device ref pcie_rp4 on end # W/A to FSP issue
|
||||||
|
device ref pcie_rp5 on end
|
||||||
|
device ref pcie_rp6 on end
|
||||||
|
device ref pcie_rp8 on end
|
||||||
|
device ref pcie_rp9 on end
|
||||||
|
device ref pcie_rp11 on end
|
||||||
|
device ref uart0 on end
|
||||||
|
device ref gspi0 on end
|
||||||
|
device ref p2sb on end
|
||||||
|
device ref hda on
|
||||||
|
chip drivers/intel/soundwire
|
||||||
|
device generic 0 on
|
||||||
|
chip drivers/soundwire/alc711
|
||||||
|
# SoundWire Link 0 ID 1
|
||||||
|
register "desc" = ""Headset Codec""
|
||||||
|
device generic 0.1 on end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
device ref smbus on end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
@ -0,0 +1,4 @@
|
||||||
|
chip soc/intel/alderlake
|
||||||
|
|
||||||
|
device domain 0 on end
|
||||||
|
end
|
||||||
|
|
@ -0,0 +1,61 @@
|
||||||
|
chip soc/intel/alderlake
|
||||||
|
|
||||||
|
device domain 0 on
|
||||||
|
device ref pch_espi on
|
||||||
|
chip ec/google/chromeec
|
||||||
|
use conn0 as mux_conn[0]
|
||||||
|
use conn1 as mux_conn[1]
|
||||||
|
use conn2 as mux_conn[2]
|
||||||
|
device pnp 0c09.0 on end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
device ref tcss_xhci on
|
||||||
|
chip drivers/usb/acpi
|
||||||
|
register "type" = "UPC_TYPE_HUB"
|
||||||
|
device ref tcss_root_hub on
|
||||||
|
chip drivers/usb/acpi
|
||||||
|
register "desc" = ""TypeC Port 1""
|
||||||
|
device ref tcss_usb3_port1 on end
|
||||||
|
end
|
||||||
|
chip drivers/usb/acpi
|
||||||
|
register "desc" = ""TypeC Port 2""
|
||||||
|
device ref tcss_usb3_port2 on end
|
||||||
|
end
|
||||||
|
chip drivers/usb/acpi
|
||||||
|
register "desc" = ""TypeC Port 3""
|
||||||
|
device ref tcss_usb3_port3 on end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
device ref pmc hidden
|
||||||
|
# The pmc_mux chip driver is a placeholder for the
|
||||||
|
# PMC.MUX device in the ACPI hierarchy.
|
||||||
|
chip drivers/intel/pmc_mux
|
||||||
|
device generic 0 on
|
||||||
|
chip drivers/intel/pmc_mux/conn
|
||||||
|
register "usb2_port_number" = "1"
|
||||||
|
register "usb3_port_number" = "1"
|
||||||
|
# SBU is fixed, HSL follows CC
|
||||||
|
register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL"
|
||||||
|
device generic 0 alias conn0 on end
|
||||||
|
end
|
||||||
|
chip drivers/intel/pmc_mux/conn
|
||||||
|
register "usb2_port_number" = "2"
|
||||||
|
register "usb3_port_number" = "2"
|
||||||
|
# SBU is fixed, HSL follows CC
|
||||||
|
register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL"
|
||||||
|
device generic 1 alias conn1 on end
|
||||||
|
end
|
||||||
|
chip drivers/intel/pmc_mux/conn
|
||||||
|
register "usb2_port_number" = "3"
|
||||||
|
register "usb3_port_number" = "3"
|
||||||
|
# SBU is fixed, HSL follows CC
|
||||||
|
register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL"
|
||||||
|
device generic 2 alias conn2 on end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
end
|
||||||
Loading…
Reference in New Issue