soc/amd/common/block/psp: move psp_notify_dram to psp_gen1.c
The MBOX_BIOS_CMD_DRAM_INFO PSP mailbox command is only available on the first generation of PSP mailbox interface and not on the second generation. The second generation of the PSP mailbox interface was introduced with the AMD family 17h SoCs on which the DRAM is already initialized before the x86 cores are released from reset. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I97b29fdc4a71d6493ec63fa60f580778f026ec0b Reviewed-on: https://review.coreboot.org/c/coreboot/+/60124 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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@ -51,6 +51,8 @@ void soc_fill_smm_reg_info(struct smm_register_info *reg); /* v2 only */
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#define PSPSTS_INVALID_NAME 8
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#define PSPSTS_INVALID_BLOB 9
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/* PSP gen1-only. SoCs with PSP gen2 already have the DRAM initialized when
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the x86 cores are released from reset. */
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int psp_notify_dram(void);
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int psp_notify_smm(void);
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@ -55,29 +55,6 @@ void psp_print_cmd_status(int cmd_status, struct mbox_buffer_header *header)
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printk(BIOS_DEBUG, "OK\n");
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}
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/*
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* Notify the PSP that DRAM is present. Upon receiving this command, the PSP
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* will load its OS into fenced DRAM that is not accessible to the x86 cores.
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*/
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int psp_notify_dram(void)
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{
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int cmd_status;
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struct mbox_default_buffer buffer = {
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.header = {
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.size = sizeof(buffer)
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}
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};
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printk(BIOS_DEBUG, "PSP: Notify that DRAM is available... ");
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cmd_status = send_psp_command(MBOX_BIOS_CMD_DRAM_INFO, &buffer);
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/* buffer's status shouldn't change but report it if it does */
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psp_print_cmd_status(cmd_status, &buffer.header);
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return cmd_status;
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}
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/*
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* Notify the PSP that the system is completing the boot process. Upon
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* receiving this command, the PSP will only honor commands where the buffer
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@ -8,7 +8,6 @@
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#include <amdblocks/psp.h>
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/* x86 to PSP commands */
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#define MBOX_BIOS_CMD_DRAM_INFO 0x01
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#define MBOX_BIOS_CMD_SMM_INFO 0x02
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#define MBOX_BIOS_CMD_SX_INFO 0x03
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#define MBOX_BIOS_CMD_SX_INFO_SLEEP_TYPE_MAX 0x07
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@ -19,7 +18,8 @@
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#define MBOX_BIOS_CMD_S3_DATA_INFO 0x08
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#define MBOX_BIOS_CMD_NOP 0x09
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#define MBOX_BIOS_CMD_ABORT 0xfe
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/* x86 to PSP commands, v1 */
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/* x86 to PSP commands, v1-only */
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#define MBOX_BIOS_CMD_DRAM_INFO 0x01
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#define MBOX_BIOS_CMD_SMU_FW 0x19
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#define MBOX_BIOS_CMD_SMU_FW2 0x1a
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@ -170,3 +170,26 @@ int psp_load_named_blob(enum psp_blob_type type, const char *name)
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cbfs_unmap(blob);
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return cmd_status;
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}
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/*
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* Notify the PSP that DRAM is present. Upon receiving this command, the PSP
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* will load its OS into fenced DRAM that is not accessible to the x86 cores.
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*/
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int psp_notify_dram(void)
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{
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int cmd_status;
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struct mbox_default_buffer buffer = {
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.header = {
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.size = sizeof(buffer)
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}
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};
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printk(BIOS_DEBUG, "PSP: Notify that DRAM is available... ");
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cmd_status = send_psp_command(MBOX_BIOS_CMD_DRAM_INFO, &buffer);
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/* buffer's status shouldn't change but report it if it does */
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psp_print_cmd_status(cmd_status, &buffer.header);
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return cmd_status;
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}
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