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mb/google/brya/variants/primus: update for next build phase 

According to the schematic diagram of version C14_MB_20210902A_SB,
modify the settings of GPIO and fw_config.

BUG=b:197700276
BRANCH=none
TEST=emerge-brya coreboot

Signed-off-by: Malik_Hsu <malik_hsu@wistron.corp-partner.google.com>
Change-Id: I14907faeb631193715b1e0e451e427fb79a68279
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57331
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Malik_Hsu 2021-09-08 09:26:40 +08:00 committed by Patrick Georgi
parent fe2d0ec029
commit e42634b059
2 changed files with 46 additions and 24 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

56
src/mainboard/google/brya/variants/primus/fw_config.c
View File

@ -6,14 +6,17 @@
#include <gpio.h> #include <gpio.h>
static const struct pad_config dmic_enable_pads[] = { static const struct pad_config dmic_enable_pads[] = {
PAD_CFG_NF(GPP_S2, NONE, DEEP, NF2), /* DMIC_CLK0_R */ PAD_CFG_NF(GPP_R4, NONE, DEEP, NF3), /* DMIC_CLK0_R */
PAD_CFG_NF(GPP_S3, NONE, DEEP, NF2), /* DMIC_DATA0_R */ PAD_CFG_NF(GPP_R5, NONE, DEEP, NF3), /* DMIC_DATA0_R */
PAD_CFG_NF(GPP_R6, NONE, DEEP, NF3), /* DMIC_CLK1_R */
PAD_CFG_NF(GPP_R7, NONE, DEEP, NF3), /* DMIC_DATA1_R */
}; };
static const struct pad_config dmic_disable_pads[] = { static const struct pad_config dmic_disable_pads[] = {
PAD_NC(GPP_S2, NONE), PAD_NC(GPP_R4, NONE),
PAD_NC(GPP_S3, NONE), PAD_NC(GPP_R5, NONE),
PAD_NC(GPP_R6, NONE),
PAD_NC(GPP_R7, NONE),
}; };
static const struct pad_config i2s_enable_pads[] = { static const struct pad_config i2s_enable_pads[] = {
@ -21,10 +24,10 @@ static const struct pad_config i2s_enable_pads[] = {
PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2), /* I2S_HP_SFRM_R */ PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2), /* I2S_HP_SFRM_R */
PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2), /* I2S_PCH_TX_HP_RX_STRAP */ PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2), /* I2S_PCH_TX_HP_RX_STRAP */
PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2), /* I2S_PCH_RX_HP_TX */ PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2), /* I2S_PCH_RX_HP_TX */
PAD_CFG_NF(GPP_R4, NONE, DEEP, NF2), /* I2S_SPKR_SCLK_R */ PAD_CFG_NF(GPP_S0, NONE, DEEP, NF4), /* I2S_SPKR_SCLK_R */
PAD_CFG_NF(GPP_R5, NONE, DEEP, NF2), /* I2S_SPKR_SFRM_R */ PAD_CFG_NF(GPP_S1, NONE, DEEP, NF4), /* I2S_SPKR_SFRM_R */
PAD_CFG_NF(GPP_R6, NONE, DEEP, NF2), /* I2S_PCH_TX_SPKR_RX_R */ PAD_CFG_NF(GPP_S2, NONE, DEEP, NF4), /* I2S_PCH_TX_SPKR_RX_R */
PAD_CFG_NF(GPP_R7, NONE, DEEP, NF2), /* I2S_PCH_RX_SPKR_TX */ PAD_CFG_NF(GPP_S3, NONE, DEEP, NF4), /* I2S_PCH_RX_SPKR_TX */
}; };
static const struct pad_config i2s_disable_pads[] = { static const struct pad_config i2s_disable_pads[] = {
@ -32,25 +35,50 @@ static const struct pad_config i2s_disable_pads[] = {
PAD_NC(GPP_R1, NONE), PAD_NC(GPP_R1, NONE),
PAD_NC(GPP_R2, NONE), PAD_NC(GPP_R2, NONE),
PAD_NC(GPP_R3, NONE), PAD_NC(GPP_R3, NONE),
PAD_NC(GPP_R4, NONE), PAD_NC(GPP_S0, NONE),
PAD_NC(GPP_R5, NONE), PAD_NC(GPP_S1, NONE),
PAD_NC(GPP_R6, NONE), PAD_NC(GPP_S2, NONE),
PAD_NC(GPP_R7, NONE), PAD_NC(GPP_S3, NONE),
}; };
static const struct pad_config bt_i2s_enable_pads[] = {
PAD_CFG_NF(GPP_VGPIO_30, NONE, DEEP, NF3), /* BT_I2S_BCLK */
PAD_CFG_NF(GPP_VGPIO_31, NONE, DEEP, NF3), /* BT_I2S_SYNC */
PAD_CFG_NF(GPP_VGPIO_32, NONE, DEEP, NF3), /* BT_I2S_SDO */
PAD_CFG_NF(GPP_VGPIO_33, NONE, DEEP, NF3), /* BT_I2S_SDI */
PAD_CFG_NF(GPP_VGPIO_34, NONE, DEEP, NF1), /* SSP2_SCLK */
PAD_CFG_NF(GPP_VGPIO_35, NONE, DEEP, NF1), /* SSP2_SFRM */
PAD_CFG_NF(GPP_VGPIO_36, NONE, DEEP, NF1), /* SSP_TXD */
PAD_CFG_NF(GPP_VGPIO_37, NONE, DEEP, NF1), /* SSP_RXD */
};
static const struct pad_config bt_i2s_disable_pads[] = {
PAD_NC(GPP_VGPIO_30, NONE),
PAD_NC(GPP_VGPIO_31, NONE),
PAD_NC(GPP_VGPIO_32, NONE),
PAD_NC(GPP_VGPIO_33, NONE),
PAD_NC(GPP_VGPIO_34, NONE),
PAD_NC(GPP_VGPIO_35, NONE),
PAD_NC(GPP_VGPIO_36, NONE),
PAD_NC(GPP_VGPIO_37, NONE),
};
static void fw_config_handle(void *unused) static void fw_config_handle(void *unused)
{ {
if (!fw_config_is_provisioned() || fw_config_probe(FW_CONFIG(AUDIO, AUDIO_UNKNOWN))) { if (!fw_config_is_provisioned() || fw_config_probe(FW_CONFIG(AUDIO, AUDIO_UNKNOWN))) {
printk(BIOS_INFO, "Disable audio related GPIO pins.\n"); printk(BIOS_INFO, "Disable audio related GPIO pins.\n");
gpio_configure_pads(i2s_disable_pads, ARRAY_SIZE(i2s_disable_pads)); gpio_configure_pads(i2s_disable_pads, ARRAY_SIZE(i2s_disable_pads));
gpio_configure_pads(dmic_disable_pads, ARRAY_SIZE(dmic_disable_pads)); gpio_configure_pads(dmic_disable_pads, ARRAY_SIZE(dmic_disable_pads));
gpio_configure_pads(bt_i2s_disable_pads, ARRAY_SIZE(bt_i2s_disable_pads));
return; return;
} }
if (fw_config_probe(FW_CONFIG(AUDIO, MAX98360_ALC5682I_I2S))) { if (fw_config_probe(FW_CONFIG(AUDIO, MAX98360_ALC5682I_I2S))) {
printk(BIOS_INFO, "Configure audio over I2S with MAX98357 ALC5682I.\n"); printk(BIOS_INFO, "Configure audio over I2S with MAX98360 ALC5682I.\n");
gpio_configure_pads(dmic_enable_pads, ARRAY_SIZE(dmic_enable_pads)); gpio_configure_pads(dmic_enable_pads, ARRAY_SIZE(dmic_enable_pads));
gpio_configure_pads(i2s_enable_pads, ARRAY_SIZE(i2s_enable_pads)); gpio_configure_pads(i2s_enable_pads, ARRAY_SIZE(i2s_enable_pads));
gpio_configure_pads(bt_i2s_enable_pads, ARRAY_SIZE(bt_i2s_enable_pads));
} }
} }
BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, fw_config_handle, NULL); BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, fw_config_handle, NULL);

14
src/mainboard/google/brya/variants/primus/gpio.c
View File

@ -10,6 +10,8 @@
static const struct pad_config override_gpio_table[] = { static const struct pad_config override_gpio_table[] = {
/* A6 : ESPI_ALERT1# ==> NC */ /* A6 : ESPI_ALERT1# ==> NC */
PAD_NC(GPP_A6, NONE), PAD_NC(GPP_A6, NONE),
/* A7 : SRCCLK_OE7# ==> NC */
PAD_NC(GPP_A7, NONE),
/* A14 : USB_OC1# ==> NC */ /* A14 : USB_OC1# ==> NC */
PAD_NC(GPP_A14, NONE), PAD_NC(GPP_A14, NONE),
/* A15 : USB_OC2# ==> NC */ /* A15 : USB_OC2# ==> NC */
@ -44,14 +46,8 @@ static const struct pad_config override_gpio_table[] = {
PAD_NC(GPP_E3, NONE), PAD_NC(GPP_E3, NONE),
/* E7 : PROC_GP1 ==> NC */ /* E7 : PROC_GP1 ==> NC */
PAD_NC(GPP_E7, NONE), PAD_NC(GPP_E7, NONE),
/* E10 : THC0_SPI1_CS# ==> NC */
PAD_NC(GPP_E10, NONE),
/* E17 : THC0_SPI1_INT# ==> NC */
PAD_NC(GPP_E17, NONE),
/* E20 : USB_C1_LSX_SOC_TX ==> EN_PP3300_eMMC */ /* E20 : USB_C1_LSX_SOC_TX ==> EN_PP3300_eMMC */
PAD_CFG_GPO(GPP_E20, 1, DEEP), PAD_CFG_GPO(GPP_E20, 1, DEEP),
/* E21 : USB_C1_LSX_SOC_RX_STRAP ==> NC */
PAD_NC(GPP_E21, NONE),
/* F19 : SRCCLKREQ6# ==> EMMC_CLKREQ_ODL */ /* F19 : SRCCLKREQ6# ==> EMMC_CLKREQ_ODL */
PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
@ -64,11 +60,9 @@ static const struct pad_config override_gpio_table[] = {
PAD_NC(GPP_H21, NONE), PAD_NC(GPP_H21, NONE),
/* H22 : IMGCLKOUT3 ==> NC */ /* H22 : IMGCLKOUT3 ==> NC */
PAD_NC(GPP_H22, NONE), PAD_NC(GPP_H22, NONE),
/* H23 : SRCCLKREQ5# ==> NC */
PAD_NC(GPP_H23, NONE),
/* S4 : SNDW2_CLK ==> NC */
PAD_NC(GPP_S4, NONE),
/* S5 : SNDW2_DATA ==> NC */
PAD_NC(GPP_S5, NONE),
/* S6 : SNDW3_CLK ==> NC */ /* S6 : SNDW3_CLK ==> NC */
PAD_NC(GPP_S6, NONE), PAD_NC(GPP_S6, NONE),
/* S7 : SNDW3_DATA ==> NC */ /* S7 : SNDW3_DATA ==> NC */