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soc/intel/lpc: Set up default LPC decode ranges 

Intel LPC devices have generic and fix IO decode ranges. This CL is
smarter about using generic ones, by using the fixed ones first.

Change-Id: Ifd98bcc639ee08d068956a33b0e12cc70211ca2d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65097
Reviewed-by: Marvin Drees <marvin.drees@9elements.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Arthur Heymans 2022-06-11 16:56:24 +02:00 committed by Martin L Roth
parent cee275fd5c
commit e4459b3961
2 changed files with 82 additions and 0 deletions
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4
src/soc/intel/common/block/lpc/lpc_def.h
View File

@ -7,6 +7,10 @@
#define LPC_SCNT_EN (1 << 7)
#define LPC_SCNT_MODE (1 << 6)
#define LPC_IO_DECODE 0x80
#define LPC_IOD_FDD_RANGE (0 << 12)
#define LPC_IOD_FDD_RANGE_MASK (1 << 12)
#define LPC_IOD_LPT_RANGE (0 << 8)
#define LPC_IOD_LPT_RANGE_MASK (3 << 8)
#define LPC_IOD_COMA_RANGE_MASK (7 << 0)
#define LPC_IOD_COMB_RANGE_MASK (7 << 4)
#define LPC_IOD_COMA_RANGE (0 << 0) /* 0x3F8 - 0x3FF COMA */

78
src/soc/intel/common/block/lpc/lpc_lib.c
View File

@ -74,6 +74,84 @@ void lpc_open_pmio_window(uint16_t base, uint16_t size)
uint32_t lgir_reg_offset, lgir, window_size, alignment;
resource_t bridged_size, bridge_base;
switch (base) {
case 0:
printk(BIOS_ERR, "LPC IO decode base 0!\n");
return;
case 0x2e:
case 0x2f:
if (size > 2)
break;
printk(BIOS_DEBUG, "LPC: enabling default decode range LPC_IOE_SUPERIO_2E_2F\n");
pci_or_config16(PCH_DEV_LPC, LPC_IO_ENABLES, LPC_IOE_SUPERIO_2E_2F);
return;
case 0x4e:
case 0x4f:
if (size > 2)
break;
printk(BIOS_DEBUG, "LPC: enabling default decode range LPC_IOE_EC_4E_4F\n");
pci_or_config16(PCH_DEV_LPC, LPC_IO_ENABLES, LPC_IOE_EC_4E_4F);
return;
case 0x60:
case 0x64:
if (size > 1)
break;
printk(BIOS_DEBUG, "LPC: enabling default decode range LPC_IOE_KBC_60_64\n");
pci_or_config16(PCH_DEV_LPC, LPC_IO_ENABLES, LPC_IOE_KBC_60_64);
return;
case 0x62:
case 0x66:
if (size > 1)
break;
printk(BIOS_DEBUG, "LPC: enabling default decode range LPC_IOE_EC_62_66\n");
pci_or_config16(PCH_DEV_LPC, LPC_IO_ENABLES, LPC_IOE_EC_62_66);
return;
case 0x200:
if (size > 8)
break;
printk(BIOS_DEBUG, "LPC: enabling default decode range LPC_IOE_LGE_200\n");
pci_or_config16(PCH_DEV_LPC, LPC_IO_ENABLES, LPC_IOE_LGE_200);
return;
case 0x208:
if (size > 8)
break;
printk(BIOS_DEBUG, "LPC: enabling default decode range LPC_IOE_HGE_208\n");
pci_or_config16(PCH_DEV_LPC, LPC_IO_ENABLES, LPC_IOE_HGE_208);
return;
case 0x2f8: /* Don't support secondary ranges */
if (size > 8)
break;
printk(BIOS_DEBUG, "LPC: enabling default decode range LPC_IOE_COMB_EN\n");
pci_or_config16(PCH_DEV_LPC, LPC_IO_ENABLES, LPC_IOE_COMB_EN);
pci_update_config16(PCH_DEV_LPC, LPC_IO_DECODE, ~LPC_IOD_COMB_RANGE_MASK,
LPC_IOD_COMB_RANGE);
return;
case 0x378: /* Don't support secondary ranges */
if (size > 8)
break;
printk(BIOS_DEBUG, "LPC: enabling default decode range LPC_IOE_LPT_EN\n");
pci_or_config16(PCH_DEV_LPC, LPC_IO_ENABLES, LPC_IOE_HGE_208);
pci_update_config16(PCH_DEV_LPC, LPC_IO_DECODE, ~LPC_IOD_LPT_RANGE_MASK,
LPC_IOD_LPT_RANGE);
return;
case 0x3f0: /* Don't support secondary ranges */
if (size > 8)
break;
printk(BIOS_DEBUG, "LPC: enabling default decode range LPC_IOE_FDD_EN\n");
pci_or_config16(PCH_DEV_LPC, LPC_IO_ENABLES, LPC_IOE_FDD_EN);
pci_update_config16(PCH_DEV_LPC, LPC_IO_DECODE, ~LPC_IOD_FDD_RANGE_MASK,
LPC_IOD_FDD_RANGE);
return;
case 0x3f8: /* Don't support secondary ranges */
if (size > 8)
break;
printk(BIOS_DEBUG, "LPC: enabling default decode range LPC_IOE_COMA_EN\n");
pci_or_config16(PCH_DEV_LPC, LPC_IO_ENABLES, LPC_IOE_COMA_EN);
pci_update_config16(PCH_DEV_LPC, LPC_IO_DECODE, ~LPC_IOD_COMA_RANGE_MASK,
LPC_IOD_COMA_RANGE);
return;
}
printk(BIOS_SPEW, "LPC: Trying to open IO window from %x size %x\n",
base, size);