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Drop VIA Epia mainboard 

.. and also drop the northbridge and southbridge used by the board.
This is one of the last boards to not use ROMCC for romstage. Let's
get rid of it.

Change-Id: I0a864b2c4ce3eeb7d3e199944eedef0cd71a85e6
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/7853
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
This commit is contained in:
Stefan Reinauer 2014-12-17 13:31:54 -08:00 committed by Stefan Reinauer
parent 5878bbd935
commit e4c73bb5ba
29 changed files with 0 additions and 1815 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
src/mainboard/via/Kconfig
View File

@ -3,8 +3,6 @@ if VENDOR_VIA
choice
prompt "Mainboard model"
config BOARD_VIA_EPIA
bool "EPIA"
config BOARD_VIA_EPIA_CN
bool "EPIA-CN"
config BOARD_VIA_EPIA_M700
@ -29,7 +27,6 @@ config BOARD_VIA_VT8454C
endchoice
source "src/mainboard/via/epia/Kconfig"
source "src/mainboard/via/epia-cn/Kconfig"
source "src/mainboard/via/epia-m700/Kconfig"
source "src/mainboard/via/epia-m850/Kconfig"

26
src/mainboard/via/epia/Kconfig
View File

@ -1,26 +0,0 @@
if BOARD_VIA_EPIA
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select CPU_VIA_C3
select NORTHBRIDGE_VIA_VT8601
select SOUTHBRIDGE_VIA_VT8231
select SUPERIO_WINBOND_W83627HF
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select BOARD_ROMSIZE_KB_256
select ROMCC
config MAINBOARD_DIR
string
default via/epia
config MAINBOARD_PART_NUMBER
string
default "EPIA"
config IRQ_SLOT_COUNT
int
default 5
endif # BOARD_VIA_EPIA

2
src/mainboard/via/epia/board_info.txt
View File

@ -1,2 +0,0 @@
Category: mini
Board URL: http://www.via.com.tw/en/products/mainboards/motherboards.jsp?motherboard_id=21

72
src/mainboard/via/epia/cmos.layout
View File

@ -1,72 +0,0 @@
entries
#start-bit length config config-ID name
#0 8 r 0 seconds
#8 8 r 0 alarm_seconds
#16 8 r 0 minutes
#24 8 r 0 alarm_minutes
#32 8 r 0 hours
#40 8 r 0 alarm_hours
#48 8 r 0 day_of_week
#56 8 r 0 day_of_month
#64 8 r 0 month
#72 8 r 0 year
#80 4 r 0 rate_select
#84 3 r 0 REF_Clock
#87 1 r 0 UIP
#88 1 r 0 auto_switch_DST
#89 1 r 0 24_hour_mode
#90 1 r 0 binary_values_enable
#91 1 r 0 square-wave_out_enable
#92 1 r 0 update_finished_enable
#93 1 r 0 alarm_interrupt_enable
#94 1 r 0 periodic_interrupt_enable
#95 1 r 0 disable_clock_updates
#96 288 r 0 temporary_filler
0 384 r 0 reserved_memory
384 1 e 4 boot_option
385 1 e 4 last_boot
386 1 e 1 ECC_memory
388 4 r 0 reboot_bits
392 3 e 5 baud_rate
400 1 e 1 power_on_after_fail
412 4 e 6 debug_level
416 4 e 7 boot_first
420 4 e 7 boot_second
424 4 e 7 boot_third
428 4 h 0 boot_index
432 8 h 0 boot_countdown
1008 16 h 0 check_sum
enumerations
#ID value text
1 0 Disable
1 1 Enable
2 0 Enable
2 1 Disable
4 0 Fallback
4 1 Normal
5 0 115200
5 1 57600
5 2 38400
5 3 19200
5 4 9600
5 5 4800
5 6 2400
5 7 1200
6 6 Notice
6 7 Info
6 8 Debug
6 9 Spew
7 0 Network
7 1 HDD
7 2 Floppy
7 8 Fallback_Network
7 9 Fallback_HDD
7 10 Fallback_Floppy
#7 3 ROM
checksums
checksum 392 1007 1008

61
src/mainboard/via/epia/devicetree.cb
View File

@ -1,61 +0,0 @@
chip northbridge/via/vt8601
device domain 0 on
device pci 0.0 on end # Northbridge
# device pci 0.1 on # AGP bridge
# device pci 0.0 on end # Integrated VGA
# end
chip southbridge/via/vt8231
register "enable_native_ide" = "0"
register "enable_com_ports" = "1"
register "enable_keyboard" = "0"
device pci 11.0 on # Southbrdge
chip superio/winbond/w83627hf
device pnp 2e.0 on # Floppy
io 0x60 = 0x3f0
irq 0x70 = 6
drq 0x74 = 2
end
device pnp 2e.1 off # Parallel Port
io 0x60 = 0x378
irq 0x70 = 7
end
device pnp 2e.2 on # Com1
io 0x60 = 0x3f8
irq 0x70 = 4
end
device pnp 2e.3 off # Com2
io 0x60 = 0x2f8
irq 0x70 = 3
end
device pnp 2e.5 on # Keyboard
io 0x60 = 0x60
io 0x62 = 0x64
irq 0x70 = 1
irq 0x72 = 12
end
end
device pnp 2e.6 off end # CIR
device pnp 2e.7 off end # GAME_MIDI_GIPO1
device pnp 2e.8 off end # GPIO2
device pnp 2e.9 off end # GPIO3
device pnp 2e.a off end # ACPI
device pnp 2e.b on # HW Monitor
io 0x60 = 0x290
end
end
device pci 11.1 on end # Ide
device pci 11.2 off end # Usb port 0-1
device pci 11.3 off end # Usb port 2-3
device pci 11.4 off end # ACPI
device pci 11.5 off end # AC97 Audio
device pci 11.6 on end # AC97 Modem
device pci 12.0 on end # Ethernet
end
end
device cpu_cluster 0 on
chip cpu/via/c3
device lapic 0 on end
end
end
end

36
src/mainboard/via/epia/irq_tables.c
View File

@ -1,36 +0,0 @@
/* This file was generated by getpir.c, do not modify!
(but if you do, please run checkpir on it to verify)
Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up
Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM
*/
#include <arch/pirq_routing.h>
static const struct irq_routing_table intel_irq_routing_table = {
PIRQ_SIGNATURE, /* u32 signature */
PIRQ_VERSION, /* u16 version */
32+16*CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */
0, /* Where the interrupt router lies (bus) */
0x88, /* Where the interrupt router lies (dev) */
0x1c20, /* IRQs devoted exclusively to PCI usage */
0x1106, /* Vendor */
0x8231, /* Device */
0, /* Miniport data */
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
0x5e, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
{
/* 8231 ethernet */
{0,0x90, {{0x1, 0xdeb8}, {0x2, 0xdeb8}, {0x3, 0xdeb8}, {0x4, 0xdeb8}}, 0x1, 0},
/* 8231 internal */
{0,0x88, {{0x2, 0xdeb8}, {0x3, 0xdeb8}, {0x4, 0xdeb8}, {0x1, 0xdeb8}}, 0x2, 0},
/* PCI slot */
{0,0xa0, {{0x3, 0xdeb8}, {0x4, 0xdeb8}, {0x1, 0xdeb8}, {0x2, 0xdeb8}}, 0, 0},
{0,0x50, {{0x4, 0xdeb8}, {0x3, 0xdeb8}, {0x2, 0xdeb8}, {0x1, 0xdeb8}}, 0x3, 0},
{0,0x98, {{0x4, 0xdeb8}, {0x3, 0xdeb8}, {0x2, 0xdeb8}, {0x1, 0xdeb8}}, 0x4, 0},
}
};
unsigned long write_pirq_routing_table(unsigned long addr)
{
return copy_pirq_routing_table(addr, &intel_irq_routing_table);
}

95
src/mainboard/via/epia/romstage.c
View File

@ -1,95 +0,0 @@
#include <stdint.h>
#include <device/pci_def.h>
#include <arch/io.h>
#include <device/pnp_def.h>
#include <stdlib.h>
#include <console/console.h>
#include "northbridge/via/vt8601/raminit.h"
#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
#include "drivers/pc80/udelay_io.c"
#include "lib/delay.c"
#include "lib/debug.c"
#include "southbridge/via/vt8231/early_smbus.c"
#include "southbridge/via/vt8231/early_serial.c"
#include "southbridge/via/vt8231/enable_rom.c"
static inline int spd_read_byte(unsigned device, unsigned address)
{
return smbus_read_byte(device, address);
}
#include "northbridge/via/vt8601/raminit.c"
static void enable_mainboard_devices(void)
{
device_t dev;
/* dev 0 for southbridge */
dev = pci_locate_device(PCI_ID(0x1106,0x8231), 0);
if (dev == PCI_DEV_INVALID)
die("Southbridge not found!!!\n");
pci_write_config8(dev, 0x50, 7);
pci_write_config8(dev, 0x51, 0xff);
#if 0
// This early setup switches IDE into compatibility mode before PCI gets
// a chance to assign I/Os
// movl $CONFIG_ADDR(0, 0x89, 0x42), %eax
// movb $0x09, %dl
// movb $0x00, %dl
// PCI_WRITE_CONFIG_BYTE
//
#endif
/* we do this here as in V2, we can not yet do raw operations
* to pci!
*/
/* changed this to work correctly on later revisions of LB.
* The original dev += 0x100; stopped working. It also appears
* that if this is not set here, but in ide_init() only, the IDE
* does not work at all. I assume it needs to be set before something else,
* possibly before enabling the IDE peripheral, or it is a timing issue.
* Ben Hewson 29 Apr 2007.
*/
dev = pci_locate_device(PCI_ID(0x1106,0x0571), 0);
pci_write_config8(dev, 0x42, 0);
}
static void enable_shadow_ram(void)
{
device_t dev = 0;
unsigned char shadowreg;
shadowreg = pci_read_config8(dev, 0x63);
/* 0xf0000-0xfffff */
shadowreg |= 0x30;
pci_write_config8(dev, 0x63, shadowreg);
}
#include <cpu/intel/romstage.h>
static void main(unsigned long bist)
{
if (bist == 0)
early_mtrr_init();
enable_vt8231_serial();
console_init();
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
vt8231_enable_rom();
enable_mainboard_devices();
enable_smbus();
enable_shadow_ram();
/*
this is way more generic than we need.
sdram_initialize(ARRAY_SIZE(cpu), cpu);
*/
sdram_set_registers((const struct mem_controller *) 0);
sdram_set_spd_registers((const struct mem_controller *) 0);
sdram_enable(0, (const struct mem_controller *) 0);
}

1
src/northbridge/via/Kconfig
View File

@ -1,7 +1,6 @@
source src/northbridge/via/cn700/Kconfig
source src/northbridge/via/cx700/Kconfig
source src/northbridge/via/cn400/Kconfig
source src/northbridge/via/vt8601/Kconfig
source src/northbridge/via/vt8623/Kconfig
source src/northbridge/via/vx800/Kconfig
source src/northbridge/via/vx900/Kconfig

1
src/northbridge/via/Makefile.inc
View File

@ -1,4 +1,3 @@
subdirs-$(CONFIG_NORTHBRIDGE_VIA_VT8601) += vt8601
subdirs-$(CONFIG_NORTHBRIDGE_VIA_VT8623) += vt8623
subdirs-$(CONFIG_NORTHBRIDGE_VIA_CN700) += cn700
subdirs-$(CONFIG_NORTHBRIDGE_VIA_CX700) += cx700

4
src/northbridge/via/vt8601/Kconfig
View File

@ -1,4 +0,0 @@
config NORTHBRIDGE_VIA_VT8601
bool
select HAVE_DEBUG_RAM_SETUP

21
src/northbridge/via/vt8601/Makefile.inc
View File

@ -1,21 +0,0 @@
##
## This file is part of the coreboot project.
##
## Copyright (C) 2007 Corey Osgood <corey.osgood@gmail.com>
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; either version 2 of the License, or
## (at your option) any later version.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
ramstage-y += northbridge.c

132
src/northbridge/via/vt8601/northbridge.c
View File

@ -1,132 +0,0 @@
#include <console/console.h>
#include <arch/io.h>
#include <stdint.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/hypertransport.h>
#include <cpu/cpu.h>
#include <cbmem.h>
#include <stdlib.h>
#include <string.h>
#include "northbridge.h"
/*
* This fixup is based on capturing values from an Award bios. Without
* this fixup the DMA write performance is awful (i.e. hdparm -t /dev/hda is 20x
* slower than normal, ethernet drops packets).
* Apparently these registers govern some sort of bus master behavior.
*/
static void northbridge_init(device_t dev)
{
printk(BIOS_SPEW, "VT8601 random fixup ...\n");
pci_write_config8(dev, 0x70, 0xc0);
pci_write_config8(dev, 0x71, 0x88);
pci_write_config8(dev, 0x72, 0xec);
pci_write_config8(dev, 0x73, 0x0c);
pci_write_config8(dev, 0x74, 0x0e);
pci_write_config8(dev, 0x75, 0x81);
pci_write_config8(dev, 0x76, 0x52);
}
static struct device_operations northbridge_operations = {
.read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = northbridge_init,
.enable = 0,
.ops_pci = 0,
};
static const struct pci_driver northbridge_driver __pci_driver = {
.ops = &northbridge_operations,
.vendor = PCI_VENDOR_ID_VIA,
.device = 0x0601, /* 0x8601 is the AGP bridge? */
};
static void pci_domain_set_resources(device_t dev)
{
static const uint8_t ramregs[] = {
0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f, 0x56, 0x57
};
device_t mc_dev;
uint32_t pci_tolm;
pci_tolm = find_pci_tolm(dev->link_list);
mc_dev = dev->link_list->children;
if (mc_dev) {
unsigned long tomk, tolmk;
unsigned char rambits;
int i, idx;
for(rambits = 0, i = 0; i < ARRAY_SIZE(ramregs); i++) {
unsigned char reg;
reg = pci_read_config8(mc_dev, ramregs[i]);
/* these are ENDING addresses, not sizes.
* if there is memory in this slot, then reg will be > rambits.
* So we just take the max, that gives us total.
* We take the highest one to cover for once and future coreboot
* bugs. We warn about bugs.
*/
if (reg > rambits)
rambits = reg;
if (reg < rambits)
printk(BIOS_ERR, "ERROR! register 0x%x is not set!\n",
ramregs[i]);
}
printk(BIOS_DEBUG, "I would set ram size to 0x%x Kbytes\n", (rambits)*8*1024);
tomk = rambits*8*1024;
/* Compute the top of Low memory */
tolmk = pci_tolm >> 10;
if (tolmk >= tomk) {
/* The PCI hole does does not overlap the memory.
*/
tolmk = tomk;
}
set_top_of_ram(tolmk * 1024);
/* Report the memory regions */
idx = 10;
ram_resource(dev, idx++, 0, tolmk);
}
assign_resources(dev->link_list);
}
static struct device_operations pci_domain_ops = {
.read_resources = pci_domain_read_resources,
.set_resources = pci_domain_set_resources,
.enable_resources = NULL,
.init = NULL,
.scan_bus = pci_domain_scan_bus,
.ops_pci_bus = pci_bus_default_ops,
};
static void cpu_bus_init(device_t dev)
{
initialize_cpus(dev->link_list);
}
static struct device_operations cpu_bus_ops = {
.read_resources = DEVICE_NOOP,
.set_resources = DEVICE_NOOP,
.enable_resources = DEVICE_NOOP,
.init = cpu_bus_init,
.scan_bus = 0,
};
static void enable_dev(struct device *dev)
{
/* Set the operations if it is a special bus type */
if (dev->path.type == DEVICE_PATH_DOMAIN) {
dev->ops = &pci_domain_ops;
}
else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) {
dev->ops = &cpu_bus_ops;
}
}
struct chip_operations northbridge_via_vt8601_ops = {
CHIP_NAME("VIA VT8601 Northbridge")
.enable_dev = enable_dev,
};

6
src/northbridge/via/vt8601/northbridge.h
View File

@ -1,6 +0,0 @@
#ifndef NORTHBRIDGE_VIA_VT8601_H
#define NORTHBRIDGE_VIA_VT8601_H
extern unsigned int vt8601_scan_root_bus(device_t root, unsigned int max);
#endif /* NORTHBRIDGE_VIA_VT8601_H */

392
src/northbridge/via/vt8601/raminit.c
View File

@ -1,392 +0,0 @@
#include <cpu/x86/mtrr.h>
#include "raminit.h"
/*
This software and ancillary information (herein called SOFTWARE )
called LinuxBIOS is made available under the terms described
here. The SOFTWARE has been approved for release with associated
LA-CC Number 00-34 . Unless otherwise indicated, this SOFTWARE has
been authored by an employee or employees of the University of
California, operator of the Los Alamos National Laboratory under
Contract No. W-7405-ENG-36 with the U.S. Department of Energy. The
U.S. Government has rights to use, reproduce, and distribute this
SOFTWARE. The public may copy, distribute, prepare derivative works
and publicly display this SOFTWARE without charge, provided that this
Notice and any statement of authorship are reproduced on all copies.
Neither the Government nor the University makes any warranty, express
or implied, or assumes any liability or responsibility for the use of
this SOFTWARE. If SOFTWARE is modified to produce derivative works,
such modified SOFTWARE should be clearly marked, so as not to confuse
it with the version available from LANL.
*/
/* Copyright 2000, Ron Minnich, Advanced Computing Lab, LANL
* rminnich@lanl.gov
*/
/*
* 11/26/02 - kevinh@ispiri.com - The existing comments implied that
* this didn't work yet. Therefore, I've updated it so that it works
* correctly - at least on my VIA epia motherboard. 64MB DIMM in slot 0.
*/
/* Added automatic detection of first equipped bank and its MA mapping type.
* (Rest of configuration is done in C)
* 5/19/03 by SONE Takeshi <ts1@tsn.or.jp>
*/
/* converted to C 9/2003 Ron Minnich */
#include <spd.h>
/* Set to 1 if your DIMMs are PC133 Note that I'm assuming CPU's FSB
* frequency is 133MHz. If your CPU runs at another bus speed, you
* might need to change some of register values.
*/
#ifndef DIMM_PC133
#define DIMM_PC133 0
#endif
// Set to 1 if your DIMMs are CL=2
#ifndef DIMM_CL2
#define DIMM_CL2 0
#endif
static void dimms_read(unsigned long x)
{
uint8_t c;
unsigned long eax;
volatile unsigned long y;
eax = x;
for (c = 0; c < 6; c++) {
y = *(volatile unsigned long *) eax;
eax += 0x10000000;
}
}
static void dimms_write(int x)
{
uint8_t c;
unsigned long eax = x;
for (c = 0; c < 6; c++) {
*(volatile unsigned long *) eax = 0;
eax += 0x10000000;
}
}
#if CONFIG_DEBUG_RAM_SETUP
static void dumpnorth(device_t north)
{
unsigned int r, c;
for (r = 0;; r += 16) {
print_debug_hex8(r);
print_debug(":");
for (c = 0; c < 16; c++) {
print_debug_hex8(pci_read_config8(north, r + c));
print_debug(" ");
}
print_debug("\n");
if (r >= 240)
break;
}
}
#endif
static void sdram_set_registers(const struct mem_controller *ctrl)
{
device_t north = (device_t) PCI_DEV(0, 0, 0);
print_err("vt8601 init starting\n");
print_debug_hex32(north);
print_debug(" is the north\n");
print_debug_hex16(pci_read_config16(north, 0));
print_debug(" ");
print_debug_hex16(pci_read_config16(north, 2));
print_debug("\n");
/* All we are doing now is setting initial known-good values that will
* be revised later as we read SPD
*/
// memory clk enable. We are not using ECC
pci_write_config8(north, 0x78, 0x01);
print_debug_hex8(pci_read_config8(north, 0x78));
// dram control, see the book.
#if DIMM_PC133
pci_write_config8(north, 0x68, 0x52);
#else
pci_write_config8(north, 0x68, 0x42);
#endif
// dram control, see the book.
pci_write_config8(north, 0x6B, 0x0c);
// Initial setting, 256MB in each bank, will be rewritten later.
pci_write_config8(north, 0x5A, 0x20);
print_debug_hex8(pci_read_config8(north, 0x5a));
pci_write_config8(north, 0x5B, 0x40);
pci_write_config8(north, 0x5C, 0x60);
pci_write_config8(north, 0x5D, 0x80);
pci_write_config8(north, 0x5E, 0xA0);
pci_write_config8(north, 0x5F, 0xC0);
// It seems we have to take care of these 2 registers as if
// they are bank 6 and 7.
pci_write_config8(north, 0x56, 0xC0);
pci_write_config8(north, 0x57, 0xC0);
// SDRAM in all banks
pci_write_config8(north, 0x60, 0x3F);
// DRAM timing. I'm suspicious of this
// This is for all banks, 64 is 0,1. 65 is 2,3. 66 is 4,5.
// ras precharge 4T, RAS pulse 5T
// cas2 is 0xd6, cas3 is 0xe6
// we're also backing off write pulse width to 2T, so result is 0xee
#if DIMM_CL2
pci_write_config8(north, 0x64, 0xd4);
pci_write_config8(north, 0x65, 0xd4);
pci_write_config8(north, 0x66, 0xd4);
#else // CL=3
pci_write_config8(north, 0x64, 0xe4);
pci_write_config8(north, 0x65, 0xe4);
pci_write_config8(north, 0x66, 0xe4);
#endif
// dram frequency select.
// enable 4K pages for 64M dram.
#if DIMM_PC133
pci_write_config8(north, 0x69, 0x3c);
#else
pci_write_config8(north, 0x69, 0xac);
#endif
/* IMPORTANT -- disable refresh counter */
// refresh counter, disabled.
pci_write_config8(north, 0x6A, 0x00);
// clkenable configuration. kevinh FIXME - add precharge
pci_write_config8(north, 0x6C, 0x00);
// dram read latch delay of 1 ns, MD drive 8 mA,
// high drive strength on MA[2: 13], we#, cas#, ras#
// As per Cindy Lee, set to 0x37, not 0x57
pci_write_config8(north, 0x6D, 0x7f);
}
/* slot is the dram slot. Return size of side0 in lower 16-bit,
* side1 in upper 16-bit, in units of 8MB */
static unsigned long spd_module_size(unsigned char slot)
{
/* for all the DRAMS, see if they are there and get the size of each
* module. This is just a very early first cut at sizing.
*/
/* we may run out of registers ... */
unsigned int banks, rows, cols;
unsigned int value = 0;
/* unsigned int module = ((DIMM0 + slot) << 1) + 1; */
unsigned int module = DIMM0 + slot;
/* is the module there? if byte 2 is not 4, then we'll assume it
* is useless.
*/
print_info("Slot ");
print_info_hex8(slot);
if (smbus_read_byte(module, 2) != 4) {
print_info(" is empty\n");
return 0;
}
print_info(" is SDRAM ");
banks = smbus_read_byte(module, 17);
/* we're going to assume symmetric banks. Sorry. */
cols = smbus_read_byte(module, 4) & 0xf;
rows = smbus_read_byte(module, 3) & 0xf;
/* grand total. You have rows+cols addressing, * times of banks, times
* width of data in bytes */
/* Width is assumed to be 64 bits == 8 bytes */
value = (1 << (cols + rows));
value *= banks * 8;
print_info_hex32(value);
print_info(" bytes ");
/* Return in 8MB units */
value >>= 23;
/* We should have single or double side */
if (smbus_read_byte(module, 5) == 2) {
print_info("x2");
value = (value << 16) | value;
}
print_info("\n");
return value;
}
#if 0
static int spd_num_chips(unsigned char slot)
{
unsigned int module = DIMM0 + slot;
unsigned int width;
width = smbus_read_byte(module, 13);
if (width == 0)
width = 8;
return 64 / width;
}
#endif
static void sdram_set_spd_registers(const struct mem_controller *ctrl)
{
#define T133 7
unsigned char Trp = 1, Tras = 1, casl = 2, val;
unsigned char timing = 0xe4;
/* read Trp */
val = smbus_read_byte(DIMM0, 27);
if (val < 2 * T133)
Trp = 1;
val = smbus_read_byte(DIMM0, 30);
if (val < 5 * T133)
Tras = 0;
val = smbus_read_byte(DIMM0, 18);
if (val < 8)
casl = 1;
if (val < 4)
casl = 0;
val = (Trp << 7) | (Tras << 6) | (casl << 4) | 4;
print_debug_hex8(val);
print_debug(" is the computed timing\n");
/* don't set it. Experience shows that this screwy chipset should just
* be run with the most conservative timing.
* pci_write_config8(0, 0x64, val);
*/
}
static void set_ma_mapping(device_t north, int slot, int type)
{
unsigned char reg, val;
int shift;
reg = 0x58 + slot / 2;
if (slot % 2 >= 1)
shift = 0;
else
shift = 4;
val = pci_read_config8(north, reg);
val &= ~(0xf << shift);
val |= type << shift;
pci_write_config8(north, reg, val);
}
static void sdram_enable(int controllers, const struct mem_controller *ctrl)
{
static const uint8_t ramregs[] = {
0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f, 0x56, 0x57
};
device_t north = 0;
uint32_t size, base, slot, ma;
/* begin to initialize */
// I forget why we need this, but we do
dimms_write(0xa55a5aa5);
/* set NOP */
pci_write_config8(north, 0x6C, 0x01);
print_debug("NOP\n");
/* wait 200us */
// You need to do the memory reference. That causes the nop cycle.
dimms_read(0);
udelay(400);
print_debug("PRECHARGE\n");
/* set precharge */
pci_write_config8(north, 0x6C, 0x02);
print_debug("DUMMY READS\n");
/* dummy reads */
dimms_read(0);
udelay(200);
print_debug("CBR\n");
/* set CBR */
pci_write_config8(north, 0x6C, 0x04);
/* do 8 reads and wait >100us between each - from via */
dimms_read(0);
udelay(200);
dimms_read(0);
udelay(200);
dimms_read(0);
udelay(200);
dimms_read(0);
udelay(200);
dimms_read(0);
udelay(200);
dimms_read(0);
udelay(200);
dimms_read(0);
udelay(200);
dimms_read(0);
udelay(200);
print_debug("MRS\n");
/* set MRS */
pci_write_config8(north, 0x6c, 0x03);
#if DIMM_CL2
dimms_read(0x150);
#else // CL=3
dimms_read(0x1d0);
#endif
udelay(200);
print_debug("NORMAL\n");
/* set to normal mode */
pci_write_config8(north, 0x6C, 0x08);
dimms_write(0x55aa55aa);
dimms_read(0);
udelay(200);
print_debug("set ref. rate\n");
// Set the refresh rate.
#if DIMM_PC133
pci_write_config8(north, 0x6A, 0x86);
#else
pci_write_config8(north, 0x6A, 0x65);
#endif
print_debug("enable multi-page open\n");
// enable multi-page open
pci_write_config8(north, 0x6B, 0x0d);
base = 0;
for (slot = 0; slot < 4; slot++) {
size = spd_module_size(slot);
/* side 0 */
base += size & 0xffff;
pci_write_config8(north, ramregs[2 * slot], base);
/* side 1 */
base += size >> 16;
if (base > 0xff)
base = 0xff;
pci_write_config8(north, ramregs[2 * slot + 1], base);
if (!size)
continue;
/* Read the row densities */
size = smbus_read_byte(DIMM0 + slot, 0x1f);
/* Set the MA map type.
*
* 0xa should be another option, but when
* it would be used is unknown.
*/
if (size < 16 ) /* less than 64 MB per side */
ma = 0x0;
else if (size < 32) /* less than 128MB per side */
ma = 0x8;
else if ( size < 64) /* less than 256MB per side */
ma = 0xc;
else /* 256MB or more per side */
ma = 0xe;
print_debug_hex16(ma);
print_debug(" is the MA type\n");
set_ma_mapping(north, slot, ma);
}
print_err("vt8601 done\n");
}

8
src/northbridge/via/vt8601/raminit.h
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@ -1,8 +0,0 @@
#ifndef RAMINIT_H
#define RAMINIT_H
struct mem_controller {
int empty;
};
#endif /* RAMINIT_H */

1
src/southbridge/via/Kconfig
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@ -1,4 +1,3 @@
source src/southbridge/via/k8t890/Kconfig
source src/southbridge/via/vt8231/Kconfig
source src/southbridge/via/vt8235/Kconfig
source src/southbridge/via/vt8237r/Kconfig

1
src/southbridge/via/Makefile.inc
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@ -1,4 +1,3 @@
subdirs-$(CONFIG_SOUTHBRIDGE_VIA_K8T890) += k8t890
subdirs-$(CONFIG_SOUTHBRIDGE_VIA_VT8231) += vt8231
subdirs-$(CONFIG_SOUTHBRIDGE_VIA_VT8235) += vt8235
subdirs-$(CONFIG_SOUTHBRIDGE_VIA_VT8237R) += vt8237r

22
src/southbridge/via/vt8231/Kconfig
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@ -1,22 +0,0 @@
##
## This file is part of the coreboot project.
##
## Copyright (C) 2008-2009 coresystems GmbH
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
config SOUTHBRIDGE_VIA_VT8231
bool
select HAVE_DEBUG_SMBUS

25
src/southbridge/via/vt8231/Makefile.inc
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@ -1,25 +0,0 @@
##
## This file is part of the coreboot project.
##
## Copyright (C) 2007, 2009 Rudolf Marek <r.marek@assembler.cz>
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
ramstage-y += vt8231.c
ramstage-y += lpc.c
ramstage-y += acpi.c
ramstage-y += ide.c
ramstage-y += nic.c
#ramstage-y += usb.c

43
src/southbridge/via/vt8231/acpi.c
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@ -1,43 +0,0 @@
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ops.h>
#include <device/pci_ids.h>
static void acpi_init(struct device *dev)
{
printk(BIOS_DEBUG, "Configuring VIA ACPI\n");
// Set ACPI base address to IO 0x4000
pci_write_config32(dev, 0x48, 0x4001);
// Enable ACPI access (and setup like award)
pci_write_config8(dev, 0x41, 0x84);
// Set hardware monitor base address to IO 0x6000
pci_write_config32(dev, 0x70, 0x6001);
// Enable hardware monitor (and setup like award)
pci_write_config8(dev, 0x74, 0x01);
// set IO base address to 0x5000
pci_write_config32(dev, 0x90, 0x5001);
// Enable SMBus
pci_write_config8(dev, 0xd2, 0x01);
}
static struct device_operations acpi_ops = {
.read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = acpi_init,
.enable = 0,
.ops_pci = 0,
};
static const struct pci_driver northbridge_driver __pci_driver = {
.ops = &acpi_ops,
.vendor = PCI_VENDOR_ID_VIA,
.device = PCI_DEVICE_ID_VIA_8231_4,
};

14
src/southbridge/via/vt8231/chip.h
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@ -1,14 +0,0 @@
#ifndef _SOUTHBRIDGE_VIA_VT8231
#define _SOUTHBRIDGE_VIA_VT8231
struct southbridge_via_vt8231_config {
/* enables of Non-PCI devices */
int enable_native_ide;
int enable_com_ports;
int enable_keyboard;
/* currently not parsed but needed by densitron dpx114 */
int enable_usb;
int enable_nvram;
};
#endif /* _SOUTHBRIDGE_VIA_VT8231 */

75
src/southbridge/via/vt8231/early_serial.c
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@ -1,75 +0,0 @@
#include <console/console.h>
/*
* Enable the serial evices on the VIA
*/
/* The base address is 0x15c, 0x2e, depending on config bytes */
#define SIO_BASE 0x3f0
#define SIO_DATA SIO_BASE+1
static void vt8231_writesuper(uint8_t reg, uint8_t val)
{
outb(reg, SIO_BASE);
outb(val, SIO_DATA);
}
static void vt8231_writesiobyte(uint16_t reg, uint8_t val)
{
outb(val, reg);
}
static void vt8231_writesioword(uint16_t reg, uint16_t val)
{
outw(val, reg);
}
/* regs we use: 85, and the southbridge devfn is defined by the
mainboard
*/
static void enable_vt8231_serial(void)
{
uint8_t c;
device_t dev;
post_code(0x06);
dev = pci_locate_device(PCI_ID(0x1106,0x8231), 0);
if (dev == PCI_DEV_INVALID) {
post_code(0x07);
die("Serial controller not found\n");
}
/* first, you have to enable the superio and superio config.
put a 6 reg 80
*/
c = pci_read_config8(dev, 0x50);
c |= 6;
pci_write_config8(dev, 0x50, c);
post_code(0x02);
// now go ahead and set up com1.
// set address
vt8231_writesuper(0xf4, 0xfe);
// enable serial out
vt8231_writesuper(0xf2, 7);
// That's it for the sio stuff.
// movl $SUPERIOCONFIG, %eax
// movb $9, %dl
// PCI_WRITE_CONFIG_BYTE
// set up reg to set baud rate.
vt8231_writesiobyte(0x3fb, 0x80);
// Set 115 kb
vt8231_writesioword(0x3f8, 1);
// Set 9.6 kb
// WRITESIOWORD(0x3f8, 12)
// now set no parity, one stop, 8 bits
vt8231_writesiobyte(0x3fb, 3);
// now turn on RTS, DRT
vt8231_writesiobyte(0x3fc, 3);
// Enable interrupts
vt8231_writesiobyte(0x3f9, 0xf);
// should be done. Dump a char for fun.
vt8231_writesiobyte(0x3f8, 48);
}

295
src/southbridge/via/vt8231/early_smbus.c
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@ -1,295 +0,0 @@
#define SMBUS_IO_BASE 0x5000
#define SMBHSTSTAT 0x0
#define SMBSLVSTAT 0x1
#define SMBHSTCTL 0x2
#define SMBHSTCMD 0x3
#define SMBXMITADD 0x4
#define SMBHSTDAT0 0x5
#define SMBHSTDAT1 0x6
#define SMBBLKDAT 0x7
#define SMBSLVCTL 0x8
#define SMBTRNSADD 0x9
#define SMBSLVDATA 0xa
#define SMLINK_PIN_CTL 0xe
#define SMBUS_PIN_CTL 0xf
/* Define register settings */
#define HOST_RESET 0xff
#define READ_CMD 0x01 // 1 in the 0 bit of SMBHSTADD states to READ
#define SMBUS_TIMEOUT (100*1000*10)
static void enable_smbus(void)
{
device_t dev;
unsigned char c;
/* Power management controller */
dev = pci_locate_device(PCI_ID(0x1106, 0x8235), 0);
if (dev == PCI_DEV_INVALID) {
die("SMBUS controller not found\n");
}
// set IO base address to SMBUS_IO_BASE
pci_write_config32(dev, 0x90, SMBUS_IO_BASE | 1);
// Enable SMBus
c = pci_read_config8(dev, 0xd2);
c |= 5;
pci_write_config8(dev, 0xd2, c);
/* make it work for I/O ...
*/
dev = pci_locate_device(PCI_ID(0x1106, 0x8231), 0);
c = pci_read_config8(dev, 4);
c |= 1;
pci_write_config8(dev, 4, c);
print_debug_hex8(c);
print_debug(" is the comm register\n");
print_debug("SMBus controller enabled\n");
}
static inline void smbus_delay(void)
{
outb(0x80, 0x80);
}
static int smbus_wait_until_active(void)
{
unsigned long loops;
loops = SMBUS_TIMEOUT;
do {
unsigned char val;
smbus_delay();
val = inb(SMBUS_IO_BASE + SMBHSTSTAT);
if ((val & 1)) {
break;
}
} while (--loops);
return loops ? 0 : -4;
}
static int smbus_wait_until_ready(void)
{
unsigned long loops;
loops = SMBUS_TIMEOUT;
do {
unsigned char val;
smbus_delay();
val = inb(SMBUS_IO_BASE + SMBHSTSTAT);
if ((val & 1) == 0) {
break;
}
if (loops == (SMBUS_TIMEOUT / 2)) {
outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
}
} while (--loops);
return loops ? 0 : -2;
}
static int smbus_wait_until_done(void)
{
unsigned long loops;
loops = SMBUS_TIMEOUT;
do {
unsigned char val;
smbus_delay();
val = inb(SMBUS_IO_BASE + SMBHSTSTAT);
if ((val & 1) == 0) {
break;
}
} while (--loops);
return loops ? 0 : -3;
}
#if 0
void smbus_reset(void)
{
outb(HOST_RESET, SMBUS_IO_BASE + SMBHSTSTAT);
outb(HOST_RESET, SMBUS_IO_BASE + SMBHSTSTAT);
outb(HOST_RESET, SMBUS_IO_BASE + SMBHSTSTAT);
outb(HOST_RESET, SMBUS_IO_BASE + SMBHSTSTAT);
smbus_wait_until_ready();
print_debug("After reset status ");
print_debug_hex8(inb(SMBUS_IO_BASE + SMBHSTSTAT));
print_debug("\n");
}
#endif
#if CONFIG_DEBUG_SMBUS
static void smbus_print_error(unsigned char host_status_register)
{
print_err("smbus_error: ");
print_err_hex8(host_status_register);
print_err("\n");
if (host_status_register & (1 << 4)) {
print_err("Interrupt/SMI# was Failed Bus Transaction\n");
}
if (host_status_register & (1 << 3)) {
print_err("Bus Error\n");
}
if (host_status_register & (1 << 2)) {
print_err("Device Error\n");
}
if (host_status_register & (1 << 1)) {
print_err("Interrupt/SMI# was Successful Completion\n");
}
if (host_status_register & (1 << 0)) {
print_err("Host Busy\n");
}
}
#endif
/*
* Copied from intel/i82801dbm early smbus code - suggested by rgm.
* Modifications/check against i2c-viapro driver code from linux-2.4.22
* and VT8231 Reference Docs - mw.
*/
static int smbus_read_byte(unsigned device, unsigned address)
{
unsigned char global_status_register;
unsigned char byte;
if (smbus_wait_until_ready() < 0) {
outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
if (smbus_wait_until_ready() < 0) {
return -2;
}
}
/* setup transaction */
/* disable interrupts */
outb(inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xfe, SMBUS_IO_BASE + SMBHSTCTL);
/* set the device I'm talking too */
outb(((device & 0x7f) << 1) | 1, SMBUS_IO_BASE + SMBXMITADD);
/* set the command/address... */
outb(address & 0xFF, SMBUS_IO_BASE + SMBHSTCMD);
/* set up for a byte data read */
outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xe3) | (0x2 << 2), SMBUS_IO_BASE + SMBHSTCTL);
/* clear any lingering errors, so the transaction will run */
outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
/* clear the data byte... */
outb(0, SMBUS_IO_BASE + SMBHSTDAT0);
/* start a byte read, with interrupts disabled */
outb((inb(SMBUS_IO_BASE + SMBHSTCTL) | 0x40), SMBUS_IO_BASE + SMBHSTCTL);
/* poll for it to start */
if (smbus_wait_until_active() < 0) {
return -4;
}
/* poll for transaction completion */
if (smbus_wait_until_done() < 0) {
return -3;
}
/* Ignore the Host Busy & Command Complete ? */
global_status_register = inb(SMBUS_IO_BASE + SMBHSTSTAT) & ~((1 << 1) | (1 << 0));
/* read results of transaction */
byte = inb(SMBUS_IO_BASE + SMBHSTDAT0);
if (global_status_register != 0) {
return -1;
}
return byte;
}
#if 0
/* SMBus routines borrowed from VIA's Trident Driver */
/* this works, so I am not going to touch it for now -- rgm */
static unsigned char smbus_read_byte(unsigned char devAdr, unsigned char bIndex)
{
unsigned int i;
unsigned char bData;
unsigned char sts = 0;
/* clear host status */
outb(0xff, SMBUS_IO_BASE);
/* check SMBUS ready */
for (i = 0; i < SMBUS_TIMEOUT; i++)
if ((inb(SMBUS_IO_BASE) & 0x01) == 0)
break;
/* set host command */
outb(bIndex, SMBUS_IO_BASE + 3);
/* set slave address */
outb(devAdr | 0x01, SMBUS_IO_BASE + 4);
/* start */
outb(0x48, SMBUS_IO_BASE + 2);
/* SMBUS Wait Ready */
for (i = 0; i < SMBUS_TIMEOUT; i++)
if (((sts = inb(SMBUS_IO_BASE)) & 0x01) == 0)
break;
if ((sts & ~3) != 0) {
smbus_print_error(sts);
return 0;
}
bData = inb(SMBUS_IO_BASE + 5);
return bData;
}
#endif
/* for reference, here is the fancier version which we will use at some
* point
*/
# if 0
int smbus_read_byte(unsigned device, unsigned address, unsigned char *result)
{
unsigned char host_status_register;
unsigned char byte;
reset();
smbus_wait_until_ready();
/* setup transaction */
/* disable interrupts */
outb(inb(SMBUS_IO_BASE + SMBHSTCTL) & (~1), SMBUS_IO_BASE + SMBHSTCTL);
/* set the device I'm talking too */
outb(((device & 0x7f) << 1) | 1, SMBUS_IO_BASE + SMBXMITADD);
/* set the command/address... */
outb(address & 0xFF, SMBUS_IO_BASE + SMBHSTCMD);
/* set up for a byte data read */
outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xE3) | (0x2 << 2), SMBUS_IO_BASE + SMBHSTCTL);
/* clear any lingering errors, so the transaction will run */
outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
/* clear the data byte... */
outb(0, SMBUS_IO_BASE + SMBHSTDAT0);
/* start the command */
outb((inb(SMBUS_IO_BASE + SMBHSTCTL) | 0x40), SMBUS_IO_BASE + SMBHSTCTL);
/* poll for transaction completion */
smbus_wait_until_done();
host_status_register = inb(SMBUS_IO_BASE + SMBHSTSTAT);
/* Ignore the In Use Status... */
host_status_register &= ~(1 << 6);
/* read results of transaction */
byte = inb(SMBUS_IO_BASE + SMBHSTDAT0);
smbus_print_error(byte);
*result = byte;
return host_status_register != 0x02;
}
#endif

46
src/southbridge/via/vt8231/enable_rom.c
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@ -1,46 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2010 Uwe Hermann <uwe@hermann-uwe.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <arch/io.h>
#include <device/pci_ids.h>
static void vt8231_enable_rom(void)
{
device_t dev;
dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_8231), 0);
/*
* ROM decode control register (0x43):
*
* Bit Decode range
* -----------------
* 7 0xFFFE0000-0xFFFEFFFF
* 6 0xFFF80000-0xFFFDFFFF
* 5 0xFFF00000-0xFFF7FFFF
* 4 0x000E0000-0x000EFFFF
* 3 0x000D8000-0x000DFFFF
* 2 0x000D0000-0x000D7FFF
* 1 0x000C8000-0x000CFFFF
* 0 0x000C0000-0x000C7FFF
*/
pci_write_config8(dev, 0x43, (1 << 7) | (1 << 6) | (1 << 5));
}

113
src/southbridge/via/vt8231/ide.c
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@ -1,113 +0,0 @@
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ops.h>
#include <device/pci_ids.h>
#include "chip.h"
static void ide_init(struct device *dev)
{
struct southbridge_via_vt8231_config *conf = (struct southbridge_via_vt8231_config *)dev->chip_info;
unsigned char enables;
if (!conf->enable_native_ide) {
// Run the IDE controller in 'compatibility mode - i.e. don't use PCI
// interrupts. Using PCI ints confuses linux for some reason.
/* Setting reg 0x42 here does not work. It is set in mainboard/romstage.c
* It probably can only be changed while the IDE is disabled
* or it is possibly a timing issue. Ben Hewson 29 Apr 2007.
*/
/*
printk(BIOS_INFO, "%s: enabling compatibility IDE addresses\n", __func__);
enables = pci_read_config8(dev, 0x42);
printk(BIOS_DEBUG, "enables in reg 0x42 0x%x\n", enables);
enables &= ~0xc0; // compatibility mode
pci_write_config8(dev, 0x42, enables);
enables = pci_read_config8(dev, 0x42);
printk(BIOS_DEBUG, "enables in reg 0x42 read back as 0x%x\n", enables);
*/
}
enables = pci_read_config8(dev, 0x40);
printk(BIOS_DEBUG, "enables in reg 0x40 0x%x\n", enables);
enables |= 3;
pci_write_config8(dev, 0x40, enables);
enables = pci_read_config8(dev, 0x40);
printk(BIOS_DEBUG, "enables in reg 0x40 read back as 0x%x\n", enables);
// Enable prefetch buffers
enables = pci_read_config8(dev, 0x41);
enables |= 0xf0;
pci_write_config8(dev, 0x41, enables);
// Lower thresholds (cause award does it)
enables = pci_read_config8(dev, 0x43);
enables &= ~0x0f;
enables |= 0x05;
pci_write_config8(dev, 0x43, enables);
// PIO read prefetch counter (cause award does it)
pci_write_config8(dev, 0x44, 0x18);
// Use memory read multiple
pci_write_config8(dev, 0x45, 0x1c);
// address decoding.
// we want "flexible", i.e. 1f0-1f7 etc. or native PCI
// kevinh@ispiri.com - the standard linux drivers seem ass slow when
// used in native mode - I've changed back to classic
enables = pci_read_config8(dev, 0x9);
printk(BIOS_DEBUG, "enables in reg 0x9 0x%x\n", enables);
// by the book, set the low-order nibble to 0xa.
if (conf->enable_native_ide) {
enables &= ~0xf;
// cf/cg silicon needs an 'f' here.
enables |= 0xf;
} else {
enables &= ~0x5;
}
pci_write_config8(dev, 0x9, enables);
enables = pci_read_config8(dev, 0x9);
printk(BIOS_DEBUG, "enables in reg 0x9 read back as 0x%x\n", enables);
// standard bios sets master bit.
enables = pci_read_config8(dev, 0x4);
printk(BIOS_DEBUG, "command in reg 0x4 0x%x\n", enables);
enables |= 7;
// No need for stepping - kevinh@ispiri.com
enables &= ~0x80;
pci_write_config8(dev, 0x4, enables);
enables = pci_read_config8(dev, 0x4);
printk(BIOS_DEBUG, "command in reg 0x4 reads back as 0x%x\n", enables);
if (!conf->enable_native_ide) {
// Use compatibility mode - per award bios
pci_write_config32(dev, 0x10, 0x0);
pci_write_config32(dev, 0x14, 0x0);
pci_write_config32(dev, 0x18, 0x0);
pci_write_config32(dev, 0x1c, 0x0);
// Force interrupts to use compat mode - just like Award bios
pci_write_config8(dev, 0x3d, 00);
pci_write_config8(dev, 0x3c, 0xff);
}
}
static struct device_operations ide_ops = {
.read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = ide_init,
.enable = 0,
.ops_pci = 0,
};
static const struct pci_driver northbridge_driver __pci_driver = {
.ops = &ide_ops,
.vendor = PCI_VENDOR_ID_VIA,
.device = PCI_DEVICE_ID_VIA_82C586_1,
};

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src/southbridge/via/vt8231/lpc.c
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@ -1,165 +0,0 @@
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ops.h>
#include <device/pci_ids.h>
#include <pc80/mc146818rtc.h>
#include <arch/ioapic.h>
#include "chip.h"
/* PIRQ init
*/
static const unsigned char southbridgeIrqs[4] = { 11, 5, 10, 12 };
static const unsigned char enetIrqs[4] = { 11, 5, 10, 12 };
static const unsigned char slotIrqs[4] = { 5, 10, 12, 11 };
/*
Our IDSEL mappings are as follows
PCI slot is AD31 (device 15) (00:14.0)
Southbridge is AD28 (device 12) (00:11.0)
*/
static void pci_routing_fixup(struct device *dev)
{
printk(BIOS_INFO, "%s: dev is %p\n", __func__, dev);
if (dev) {
/* initialize PCI interrupts - these assignments depend
on the PCB routing of PINTA-D
PINTA = IRQ11
PINTB = IRQ5
PINTC = IRQ10
PINTD = IRQ12
*/
pci_write_config8(dev, 0x55, 0xb0);
pci_write_config8(dev, 0x56, 0xa5);
pci_write_config8(dev, 0x57, 0xc0);
}
// Standard southbridge components
printk(BIOS_INFO, "setting southbridge\n");
pci_assign_irqs(0, 0x11, southbridgeIrqs);
// Ethernet built into southbridge
printk(BIOS_INFO, "setting ethernet\n");
pci_assign_irqs(0, 0x12, enetIrqs);
// PCI slot
printk(BIOS_INFO, "setting pci slot\n");
pci_assign_irqs(0, 0x14, slotIrqs);
printk(BIOS_INFO, "%s: DONE\n", __func__);
}
static void vt8231_init(struct device *dev)
{
unsigned char enables;
printk(BIOS_DEBUG, "vt8231 init\n");
// enable the internal I/O decode
enables = pci_read_config8(dev, 0x6C);
enables |= 0x80;
pci_write_config8(dev, 0x6C, enables);
// Set bit 6 of 0x40, because Award does it (IO recovery time)
// IMPORTANT FIX - EISA 0x4d0 decoding must be on so that PCI
// interrupts can be properly marked as level triggered.
enables = pci_read_config8(dev, 0x40);
pci_write_config8(dev, 0x40, enables);
// Set 0x42 to 0xf0 to match Award bios
enables = pci_read_config8(dev, 0x42);
enables |= 0xf0;
pci_write_config8(dev, 0x42, enables);
// Set bit 3 of 0x4a, to match award (dummy pci request)
enables = pci_read_config8(dev, 0x4a);
enables |= 0x08;
pci_write_config8(dev, 0x4a, enables);
// Set bit 3 of 0x4f to match award (use INIT# as cpu reset)
enables = pci_read_config8(dev, 0x4f);
enables |= 0x08;
pci_write_config8(dev, 0x4f, enables);
// Set 0x58 to 0x03 to match Award
pci_write_config8(dev, 0x58, 0x03);
// enable the ethernet/RTC
if (dev) {
enables = pci_read_config8(dev, 0x51);
enables |= 0x18;
pci_write_config8(dev, 0x51, enables);
}
// enable IDE, since Linux won't do it.
// First do some more things to devfn (17,0)
// note: this should already be cleared, according to the book.
enables = pci_read_config8(dev, 0x50);
printk(BIOS_DEBUG, "IDE enable in reg. 50 is 0x%x\n", enables);
enables &= ~8; // need manifest constant here!
printk(BIOS_DEBUG, "set IDE reg. 50 to 0x%x\n", enables);
pci_write_config8(dev, 0x50, enables);
// set default interrupt values (IDE)
enables = pci_read_config8(dev, 0x4c);
printk(BIOS_DEBUG, "IRQs in reg. 4c are 0x%x\n", enables & 0xf);
// clear out whatever was there.
enables &= ~0xf;
enables |= 4;
printk(BIOS_DEBUG, "setting reg. 4c to 0x%x\n", enables);
pci_write_config8(dev, 0x4c, enables);
// set up the serial port interrupts.
// com2 to 3, com1 to 4
pci_write_config8(dev, 0x46, 0x04);
pci_write_config8(dev, 0x47, 0x03);
pci_write_config8(dev, 0x6e, 0x98);
/* set up isa bus -- i/o recovery time, rom write enable, extend-ale */
pci_write_config8(dev, 0x40, 0x54);
//ethernet_fixup();
// Start the rtc
cmos_init(0);
}
static void vt8231_read_resources(device_t dev)
{
struct resource *res;
pci_dev_read_resources(dev);
res = new_resource(dev, 1);
res->base = 0x0UL;
res->size = 0x1000UL;
res->limit = 0xffffUL;
res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
res = new_resource(dev, 3); /* IOAPIC */
res->base = IO_APIC_ADDR;
res->size = 0x00001000;
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
}
static void southbridge_init(struct device *dev)
{
vt8231_init(dev);
pci_routing_fixup(dev);
}
static struct device_operations vt8231_lpc_ops = {
.read_resources = vt8231_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = &southbridge_init,
.scan_bus = scan_static_bus,
.enable = 0,
.ops_pci = 0,
};
static const struct pci_driver lpc_driver __pci_driver = {
.ops = &vt8231_lpc_ops,
.vendor = PCI_VENDOR_ID_VIA,
.device = PCI_DEVICE_ID_VIA_8231,
};

36
src/southbridge/via/vt8231/nic.c
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#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ops.h>
#include <device/pci_ids.h>
/*
* Enable the ethernet device and turn off stepping (because it is integrated
* inside the southbridge)
*/
static void nic_init(struct device *dev)
{
uint8_t byte;
printk(BIOS_DEBUG, "Configuring VIA LAN\n");
/* We don't need stepping - though the device supports it */
byte = pci_read_config8(dev, PCI_COMMAND);
byte &= ~PCI_COMMAND_WAIT;
pci_write_config8(dev, PCI_COMMAND, byte);
}
static struct device_operations nic_ops = {
.read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = nic_init,
.enable = 0,
.ops_pci = 0,
};
static const struct pci_driver northbridge_driver __pci_driver = {
.ops = &nic_ops,
.vendor = PCI_VENDOR_ID_VIA,
.device = PCI_DEVICE_ID_VIA_8233_7,
};

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src/southbridge/via/vt8231/usb.c
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static void usb_on(int enable)
{
unsigned char regval;
/* Base 8231 controller */
device_t dev0 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, 0);
/* USB controller 1 */
device_t dev2 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_2, 0);
/* USB controller 2 */
device_t dev3 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_2, dev2);
/* enable USB1 */
if(dev2) {
if (enable) {
pci_write_config8(dev2, 0x3c, 0x05);
pci_write_config8(dev2, 0x04, 0x07);
} else {
pci_write_config8(dev2, 0x3c, 0x00);
pci_write_config8(dev2, 0x04, 0x00);
}
}
if(dev0) {
regval = pci_read_config8(dev0, 0x50);
if (enable)
regval &= ~(0x10);
else
regval |= 0x10;
pci_write_config8(dev0, 0x50, regval);
}
/* enable USB2 */
if(dev3) {
if (enable) {
pci_write_config8(dev3, 0x3c, 0x05);
pci_write_config8(dev3, 0x04, 0x07);
} else {
pci_write_config8(dev3, 0x3c, 0x00);
pci_write_config8(dev3, 0x04, 0x00);
}
}
if(dev0) {
regval = pci_read_config8(dev0, 0x50);
if (enable)
regval &= ~(0x20);
else
regval |= 0x20;
pci_write_config8(dev0, 0x50, regval);
}
}

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src/southbridge/via/vt8231/vt8231.c
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#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ops.h>
#include <device/pci_ids.h>
#include <pc80/mc146818rtc.h>
#include <pc80/keyboard.h>
#include "chip.h"
/* Base 8231 controller */
static device_t lpc_dev;
static void keyboard_on(void)
{
unsigned char regval;
if (lpc_dev) {
regval = pci_read_config8(lpc_dev, 0x51);
regval |= 0x0f;
pci_write_config8(lpc_dev, 0x51, regval);
}
pc_keyboard_init();
}
static void com_port_on(void)
{
#if 0
// enable com1 and com2.
enables = pci_read_config8(dev, 0x6e);
/* 0x80 is enable com port b, 0x10 is to make it com2, 0x8
* is enable com port a as com1 kevinh/Ispiri - Old code
* thought 0x01 would make it com1, that was wrong enables =
* 0x80 | 0x10 | 0x8 ; pci_write_config8(dev, 0x6e,
* enables); // note: this is also a redo of some port of
* assembly, but we want everything up.
*/
/* set com1 to 115 kbaud not clear how to do this yet.
* forget it; done in assembly.
*/
#endif
}
/* FixME: to be removed ? */
static void vt8231_enable(struct device *dev)
{
struct southbridge_via_vt8231_config *conf = dev->chip_info;
if (!lpc_dev) {
/* the first time called, enable devices not on PCI bus
* FIXME: is that device struct there yet? */
lpc_dev = dev_find_device(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_8231, 0);
if (conf->enable_keyboard)
keyboard_on();
if (conf->enable_com_ports)
com_port_on();
}
}
struct chip_operations southbridge_via_vt8231_ops = {
CHIP_NAME("VIA VT8231 Southbridge")
.enable_dev = vt8231_enable,
};