soc/intel/cannonlake: Fix compilation
Change MicrocodeRegionLength to MicrocodeRegionSize as per coffeelake FsptUpd.h. TEST= Build with CONFIG_USE_CANNONLAKE_FSP_CAR selected and boot test on coffeelake RVP. Change-Id: Iebbf5c34e289870a4d7abdd49fd81e4db236051a Signed-off-by: Praveen Hodagatta Pranesh <praveenx.hodagatta.pranesh@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37265 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -39,10 +39,10 @@ const FSPT_UPD temp_ram_init_params = {
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* All SoC since Gen-4 has above mechanism in place to load microcode
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* even before hitting CPU reset vector. Hence skipping FSP-T loading
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* microcode after CPU reset by passing '0' value to
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* FSPT_UPD.MicrocodeRegionBase and FSPT_UPD.MicrocodeRegionLength.
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* FSPT_UPD.MicrocodeRegionBase and FSPT_UPD.MicrocodeRegionSize.
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*/
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.MicrocodeRegionBase = 0,
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.MicrocodeRegionLength = 0,
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.MicrocodeRegionSize = 0,
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.CodeRegionBase =
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(uint32_t)(0x100000000ULL - CONFIG_ROM_SIZE),
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.CodeRegionSize = (uint32_t)CONFIG_ROM_SIZE,
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