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soc/intel/cannonlake: Fix compilation 

Change MicrocodeRegionLength to MicrocodeRegionSize as per
coffeelake FsptUpd.h.

TEST= Build with CONFIG_USE_CANNONLAKE_FSP_CAR selected and boot test on
      coffeelake RVP.

Change-Id: Iebbf5c34e289870a4d7abdd49fd81e4db236051a
Signed-off-by: Praveen Hodagatta Pranesh <praveenx.hodagatta.pranesh@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37265
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Praveen Hodagatta Pranesh 2019-11-27 13:47:09 +08:00 committed by Patrick Georgi
parent b7f30ad25f
commit e58eafc45a
1 changed files with 2 additions and 2 deletions
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4
src/soc/intel/cannonlake/bootblock/bootblock.c
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@ -39,10 +39,10 @@ const FSPT_UPD temp_ram_init_params = {
* All SoC since Gen-4 has above mechanism in place to load microcode * All SoC since Gen-4 has above mechanism in place to load microcode
* even before hitting CPU reset vector. Hence skipping FSP-T loading * even before hitting CPU reset vector. Hence skipping FSP-T loading
* microcode after CPU reset by passing '0' value to * microcode after CPU reset by passing '0' value to
* FSPT_UPD.MicrocodeRegionBase and FSPT_UPD.MicrocodeRegionLength. * FSPT_UPD.MicrocodeRegionBase and FSPT_UPD.MicrocodeRegionSize.
*/ */
.MicrocodeRegionBase = 0, .MicrocodeRegionBase = 0,
.MicrocodeRegionLength = 0, .MicrocodeRegionSize = 0,
.CodeRegionBase = .CodeRegionBase =
(uint32_t)(0x100000000ULL - CONFIG_ROM_SIZE), (uint32_t)(0x100000000ULL - CONFIG_ROM_SIZE),
.CodeRegionSize = (uint32_t)CONFIG_ROM_SIZE, .CodeRegionSize = (uint32_t)CONFIG_ROM_SIZE,