soc/intel/apollolake: Clean up code by using common FAST_SPI module
This patch currently contains the following - 1. Use SOC_INTEL_COMMON_BLOCK_FAST_SPI kconfig for common FAST_SPI code. 2. Perform FAST_SPI programming by calling APIs from common FAST_SPI library. 3. Use common FAST_SPI header file. Change-Id: Ifd72734dadda541fe4c828e4f1716e532ec69c27 Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/19080 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Barnali Sarkar
Furquan Shaikh
parent
7146445be9
commit
e70142c9c2
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@ -54,6 +54,7 @@ config CPU_SPECIFIC_OPTIONS
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select SOC_INTEL_COMMON_ACPI
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select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
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select SOC_INTEL_COMMON_BLOCK
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select SOC_INTEL_COMMON_BLOCK_FAST_SPI
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select SOC_INTEL_COMMON_BLOCK_ITSS
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select SOC_INTEL_COMMON_BLOCK_LPSS
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select SOC_INTEL_COMMON_BLOCK_PCR
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@ -11,7 +11,6 @@ subdirs-y += ../../../cpu/x86/cache
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bootblock-y += bootblock/bootblock.c
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bootblock-y += bootblock/bootblock.c
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bootblock-y += car.c
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bootblock-y += flash_ctrlr.c
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bootblock-y += gpio.c
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bootblock-y += heci.c
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bootblock-y += lpc_lib.c
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@ -24,7 +23,6 @@ bootblock-$(CONFIG_FSP_CAR) += bootblock/cache_as_ram_fsp.S
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romstage-y += car.c
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romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += romstage.c
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romstage-y += flash_ctrlr.c
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romstage-y += gpio.c
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romstage-y += heci.c
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romstage-y += i2c_early.c
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@ -38,7 +36,6 @@ romstage-y += pmutil.c
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romstage-y += reset.c
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romstage-y += spi.c
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smm-y += flash_ctrlr.c
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smm-y += mmap_boot.c
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smm-y += pmutil.c
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smm-y += gpio.c
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@ -52,7 +49,6 @@ ramstage-y += cpu.c
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ramstage-y += chip.c
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ramstage-y += cse.c
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ramstage-y += elog.c
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ramstage-y += flash_ctrlr.c
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ramstage-y += dsp.c
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ramstage-y += gpio.c
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ramstage-y += graphics.c
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@ -79,7 +75,6 @@ ramstage-y += xdci.c
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ramstage-y += xhci.c
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ramstage-y += sd.c
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postcar-y += flash_ctrlr.c
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postcar-y += memmap.c
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postcar-y += mmap_boot.c
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postcar-y += spi.c
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@ -89,7 +84,6 @@ postcar-y += tsc_freq.c
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postcar-$(CONFIG_FSP_CAR) += exit_car_fsp.S
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verstage-y += car.c
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verstage-y += flash_ctrlr.c
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verstage-y += i2c_early.c
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verstage-y += heci.c
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verstage-y += memmap.c
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@ -18,13 +18,13 @@
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#include <bootblock_common.h>
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#include <cpu/x86/mtrr.h>
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#include <device/pci.h>
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#include <intelblocks/fast_spi.h>
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#include <intelblocks/pcr.h>
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#include <intelblocks/systemagent.h>
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#include <intelblocks/rtc.h>
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#include <intelblocks/systemagent.h>
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#include <lib.h>
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#include <soc/iomap.h>
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#include <soc/cpu.h>
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#include <soc/flash_ctrlr.h>
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#include <soc/gpio.h>
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#include <soc/mmap_boot.h>
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#include <soc/systemagent.h>
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@ -92,35 +92,6 @@ static void cache_bios_region(void)
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set_var_mtrr(mtrr, 4ULL*GiB - rom_size, rom_size, MTRR_TYPE_WRPROT);
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}
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/*
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* Program temporary BAR for SPI in case any of the stages before ramstage need
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* to access SPI MMIO regs. Ramstage will assign a new BAR during PCI
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* enumeration.
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*/
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static void enable_spibar(void)
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{
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device_t dev = PCH_DEV_SPI;
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uint8_t val;
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/* Disable Bus Master and MMIO space. */
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val = pci_read_config8(dev, PCI_COMMAND);
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val &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
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pci_write_config8(dev, PCI_COMMAND, val);
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/* Program Temporary BAR for SPI */
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pci_write_config32(dev, PCI_BASE_ADDRESS_0,
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PRERAM_SPI_BASE_ADDRESS |
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PCI_BASE_ADDRESS_SPACE_MEMORY);
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/* Enable Bus Master and MMIO Space */
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val = pci_read_config8(dev, PCI_COMMAND);
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val |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
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pci_write_config8(dev, PCI_COMMAND, val);
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/* Initialize SPI to allow BIOS to write/erase on flash. */
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spi_flash_init();
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}
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static void enable_pmcbar(void)
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{
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device_t pmc = PCH_DEV_PMC;
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@ -152,7 +123,7 @@ void bootblock_soc_early_init(void)
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enable_pm_timer_emulation();
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enable_spibar();
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fast_spi_early_init(PRERAM_SPI_BASE_ADDRESS);
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cache_bios_region();
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@ -24,6 +24,7 @@
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#include <cpu/x86/mp.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <intelblocks/fast_spi.h>
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#include <fsp/api.h>
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#include <fsp/util.h>
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#include <intelblocks/itss.h>
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@ -31,7 +32,6 @@
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#include <soc/iomap.h>
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#include <soc/itss.h>
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#include <soc/cpu.h>
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#include <soc/flash_ctrlr.h>
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#include <soc/intel/common/vbt.h>
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#include <soc/nvs.h>
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#include <soc/pci_devs.h>
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@ -578,7 +578,7 @@ void platform_fsp_notify_status(enum fsp_notify_phase phase)
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*/
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static void spi_flash_init_cb(void *unused)
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{
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spi_flash_init();
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fast_spi_init();
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}
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BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, spi_flash_init_cb, NULL);
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@ -1,391 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2016 Intel Corp.
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* (Written by Alexandru Gagniuc <alexandrux.gagniuc@intel.com> for Intel Corp.)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#define __SIMPLE_DEVICE__
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#include <arch/early_variables.h>
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#include <arch/io.h>
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <soc/flash_ctrlr.h>
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#include <soc/intel/common/spi_flash.h>
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#include <soc/pci_devs.h>
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#include <spi_flash.h>
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#include <spi-generic.h>
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#include <stdlib.h>
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#include <string.h>
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/* Helper to create a SPI context on API entry. */
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#define BOILERPLATE_CREATE_CTX(ctx) \
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struct spi_flash_ctx real_ctx; \
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struct spi_flash_ctx *ctx = &real_ctx; \
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_get_spi_flash_ctx(ctx)
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/*
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* Anything that's not success is <0. Provided solely for readability, as these
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* constants are not used outside this file.
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*/
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enum errors {
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SUCCESS = 0,
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E_NOT_IMPLEMENTED = -1,
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E_TIMEOUT = -2,
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E_HW_ERROR = -3,
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E_ARGUMENT = -4,
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};
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/* Reduce data-passing burden by grouping transaction data in a context. */
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struct spi_flash_ctx {
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uintptr_t mmio_base;
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device_t pci_dev;
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uint32_t hsfsts_on_last_error;
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};
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static void _get_spi_flash_ctx(struct spi_flash_ctx *ctx)
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{
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uint32_t bar;
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/* FIXME: use device definition */
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ctx->pci_dev = PCH_DEV_SPI;
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bar = pci_read_config32(ctx->pci_dev, PCI_BASE_ADDRESS_0);
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ctx->mmio_base = bar & ~PCI_BASE_ADDRESS_MEM_ATTR_MASK;
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ctx->hsfsts_on_last_error = 0;
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}
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/* Read register from the SPI flash controller. 'reg' is the register offset. */
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static uint32_t _spi_flash_ctrlr_reg_read(struct spi_flash_ctx *ctx,
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uint16_t reg)
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{
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uintptr_t addr = ALIGN_DOWN(ctx->mmio_base + reg, 4);
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return read32((void *)addr);
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}
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uint32_t spi_flash_ctrlr_reg_read(uint16_t reg)
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{
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BOILERPLATE_CREATE_CTX(ctx);
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return _spi_flash_ctrlr_reg_read(ctx, reg);
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}
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/* Write to register in SPI flash controller. 'reg' is the register offset. */
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static void _spi_flash_ctrlr_reg_write(struct spi_flash_ctx *ctx, uint16_t reg,
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uint32_t val)
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{
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uintptr_t addr = ALIGN_DOWN(ctx->mmio_base + reg, 4);
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write32((void *)addr, val);
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}
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/*
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* The hardware datasheet is not clear on what HORD values actually do. It
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* seems that HORD_SFDP provides access to the first 8 bytes of the SFDP, which
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* is the signature and revision fields. HORD_JEDEC provides access to the
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* actual flash parameters, and is most likely what you want to use when
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* probing the flash from software.
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* It's okay to rely on SFPD, since the SPI flash controller requires an SFDP
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* 1.5 or newer compliant SPI flash chip.
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* NOTE: Due to the register layout of the hardware, all accesses will be
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* aligned to a 4 byte boundary.
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*/
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static uint32_t read_spi_flash_sfdp_param(struct spi_flash_ctx *ctx,
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uint16_t sfdp_reg)
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{
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uint32_t ptinx_index = sfdp_reg & SPIBAR_PTINX_IDX_MASK;
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_spi_flash_ctrlr_reg_write(ctx, SPIBAR_PTINX,
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ptinx_index | SPIBAR_PTINX_HORD_JEDEC);
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return _spi_flash_ctrlr_reg_read(ctx, SPIBAR_PTDATA);
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}
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/* Fill FDATAn FIFO in preparation for a write transaction. */
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static void fill_xfer_fifo(struct spi_flash_ctx *ctx, const void *data,
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size_t len)
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{
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len = min(len, SPIBAR_FDATA_FIFO_SIZE);
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/* YES! memcpy() works. FDATAn does not require 32-bit accesses. */
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memcpy((void *)(ctx->mmio_base + SPIBAR_FDATA(0)), data, len);
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}
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/* Drain FDATAn FIFO after a read transaction populates data. */
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static void drain_xfer_fifo(struct spi_flash_ctx *ctx, void *dest, size_t len)
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{
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len = min(len, SPIBAR_FDATA_FIFO_SIZE);
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/* YES! memcpy() works. FDATAn does not require 32-bit accesses. */
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memcpy(dest, (void *)(ctx->mmio_base + SPIBAR_FDATA(0)), len);
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}
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/* Fire up a transfer using the hardware sequencer. */
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static void start_hwseq_xfer(struct spi_flash_ctx *ctx, uint32_t hsfsts_cycle,
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uint32_t flash_addr, size_t len)
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{
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/* Make sure all W1C status bits get cleared. */
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uint32_t hsfsts = SPIBAR_HSFSTS_W1C_BITS;
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/* Set up transaction parameters. */
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hsfsts |= hsfsts_cycle & SPIBAR_HSFSTS_FCYCLE_MASK;
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hsfsts |= SPIBAR_HSFSTS_FBDC(len - 1);
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_spi_flash_ctrlr_reg_write(ctx, SPIBAR_FADDR, flash_addr);
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_spi_flash_ctrlr_reg_write(ctx, SPIBAR_HSFSTS_CTL,
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hsfsts | SPIBAR_HSFSTS_FGO);
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}
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static void print_xfer_error(struct spi_flash_ctx *ctx,
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const char *failure_reason, uint32_t flash_addr)
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{
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printk(BIOS_ERR, "SPI Transaction %s at flash offset %x.\n"
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"\tHSFSTS = 0x%08x\n",
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failure_reason, flash_addr, ctx->hsfsts_on_last_error);
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}
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static int wait_for_hwseq_xfer(struct spi_flash_ctx *ctx)
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{
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uint32_t hsfsts;
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do {
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hsfsts = _spi_flash_ctrlr_reg_read(ctx, SPIBAR_HSFSTS_CTL);
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if (hsfsts & SPIBAR_HSFSTS_FCERR) {
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ctx->hsfsts_on_last_error = hsfsts;
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return E_HW_ERROR;
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}
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/* TODO: set up timer and abort on timeout */
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} while (!(hsfsts & SPIBAR_HSFSTS_FDONE));
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return SUCCESS;
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}
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/* Execute SPI flash transfer. This is a blocking call. */
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static int exec_sync_hwseq_xfer(struct spi_flash_ctx *ctx,
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uint32_t hsfsts_cycle, uint32_t flash_addr,
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size_t len)
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{
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int ret;
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start_hwseq_xfer(ctx, hsfsts_cycle, flash_addr, len);
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ret = wait_for_hwseq_xfer(ctx);
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if (ret != SUCCESS) {
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const char *reason = (ret == E_TIMEOUT) ? "timeout" : "error";
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print_xfer_error(ctx, reason, flash_addr);
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}
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return ret;
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}
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unsigned int spi_crop_chunk(unsigned int cmd_len, unsigned int buf_len)
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{
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return MIN(buf_len, SPIBAR_FDATA_FIFO_SIZE);
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}
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/*
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* Write-protection status for BIOS region (BIOS_CONTROL register):
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* EISS/WPD bits 00 01 10 11
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* -- -- -- --
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* normal mode RO RW RO RO
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* SMM mode RO RW RO RW
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*/
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void spi_flash_init(void)
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{
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uint32_t bios_ctl;
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BOILERPLATE_CREATE_CTX(ctx);
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bios_ctl = pci_read_config32(ctx->pci_dev, SPIBAR_BIOS_CONTROL);
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bios_ctl |= SPIBAR_BIOS_CONTROL_WPD;
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bios_ctl &= ~SPIBAR_BIOS_CONTROL_EISS;
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/* Enable Prefetching and caching. */
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bios_ctl |= SPIBAR_BIOS_CONTROL_PREFETCH_ENABLE;
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bios_ctl &= ~SPIBAR_BIOS_CONTROL_CACHE_DISABLE;
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pci_write_config32(ctx->pci_dev, SPIBAR_BIOS_CONTROL, bios_ctl);
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}
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/* Flash device operations. */
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static struct spi_flash boot_flash CAR_GLOBAL;
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static int nuclear_spi_flash_erase(const struct spi_flash *flash,
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uint32_t offset, size_t len)
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{
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int ret;
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size_t erase_size;
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uint32_t erase_cycle;
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BOILERPLATE_CREATE_CTX(ctx);
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if (!IS_ALIGNED(offset, 4 * KiB) || !IS_ALIGNED(len, 4 * KiB)) {
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printk(BIOS_ERR, "BUG! SPI erase region not sector aligned.\n");
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return E_ARGUMENT;
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}
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while (len) {
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if (IS_ALIGNED(offset, 64 * KiB) && (len >= 64 * KiB)) {
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erase_size = 64 * KiB;
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erase_cycle = SPIBAR_HSFSTS_CYCLE_64K_ERASE;
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} else {
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erase_size = 4 * KiB;
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erase_cycle = SPIBAR_HSFSTS_CYCLE_4K_ERASE;
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}
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printk(BIOS_SPEW, "Erasing flash addr %x + %zu KiB\n",
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offset, erase_size / KiB);
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ret = exec_sync_hwseq_xfer(ctx, erase_cycle, offset, 0);
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if (ret != SUCCESS)
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return ret;
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offset += erase_size;
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len -= erase_size;
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}
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return SUCCESS;
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}
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/*
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* Ensure read/write xfer len is not greater than SPIBAR_FDATA_FIFO_SIZE and
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* that the operation does not cross 256-byte boundary.
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*/
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static size_t get_xfer_len(uint32_t addr, size_t len)
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{
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size_t xfer_len = min(len, SPIBAR_FDATA_FIFO_SIZE);
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size_t bytes_left = ALIGN_UP(addr, 256) - addr;
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if (bytes_left)
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xfer_len = min(xfer_len, bytes_left);
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return xfer_len;
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}
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static int nuclear_spi_flash_read(const struct spi_flash *flash, uint32_t addr,
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size_t len, void *buf)
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{
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int ret;
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size_t xfer_len;
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uint8_t *data = buf;
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||||
|
||||
BOILERPLATE_CREATE_CTX(ctx);
|
||||
|
||||
while (len) {
|
||||
xfer_len = get_xfer_len(addr, len);
|
||||
|
||||
ret = exec_sync_hwseq_xfer(ctx, SPIBAR_HSFSTS_CYCLE_READ,
|
||||
addr, xfer_len);
|
||||
if (ret != SUCCESS)
|
||||
return ret;
|
||||
|
||||
drain_xfer_fifo(ctx, data, xfer_len);
|
||||
|
||||
addr += xfer_len;
|
||||
data += xfer_len;
|
||||
len -= xfer_len;
|
||||
}
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
static int nuclear_spi_flash_write(const struct spi_flash *flash, uint32_t addr,
|
||||
size_t len, const void *buf)
|
||||
{
|
||||
int ret;
|
||||
size_t xfer_len;
|
||||
const uint8_t *data = buf;
|
||||
|
||||
BOILERPLATE_CREATE_CTX(ctx);
|
||||
|
||||
while (len) {
|
||||
xfer_len = get_xfer_len(addr, len);
|
||||
fill_xfer_fifo(ctx, data, xfer_len);
|
||||
|
||||
ret = exec_sync_hwseq_xfer(ctx, SPIBAR_HSFSTS_CYCLE_WRITE,
|
||||
addr, xfer_len);
|
||||
if (ret != SUCCESS)
|
||||
return ret;
|
||||
|
||||
addr += xfer_len;
|
||||
data += xfer_len;
|
||||
len -= xfer_len;
|
||||
}
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
static int nuclear_spi_flash_status(const struct spi_flash *flash, uint8_t *reg)
|
||||
{
|
||||
int ret;
|
||||
BOILERPLATE_CREATE_CTX(ctx);
|
||||
|
||||
ret = exec_sync_hwseq_xfer(ctx, SPIBAR_HSFSTS_CYCLE_RD_STATUS, 0,
|
||||
sizeof(*reg));
|
||||
if (ret != SUCCESS)
|
||||
return ret;
|
||||
|
||||
drain_xfer_fifo(ctx, reg, sizeof(*reg));
|
||||
return ret;
|
||||
}
|
||||
|
||||
/*
|
||||
* We can't use FDOC and FDOD to read FLCOMP, as previous platforms did.
|
||||
* For details see:
|
||||
* Ch 31, SPI: p. 194
|
||||
* The size of the flash component is always taken from density field in the
|
||||
* SFDP table. FLCOMP.C0DEN is no longer used by the Flash Controller.
|
||||
*/
|
||||
struct spi_flash *spi_flash_programmer_probe(struct spi_slave *dev, int force)
|
||||
{
|
||||
BOILERPLATE_CREATE_CTX(ctx);
|
||||
struct spi_flash *flash;
|
||||
uint32_t flash_bits;
|
||||
|
||||
flash = car_get_var_ptr(&boot_flash);
|
||||
|
||||
/*
|
||||
* bytes = (bits + 1) / 8;
|
||||
* But we need to do the addition in a way which doesn't overflow for
|
||||
* 4 Gbit devices (flash_bits == 0xffffffff).
|
||||
*/
|
||||
/* FIXME: Don't hardcode 0x04 ? */
|
||||
flash_bits = read_spi_flash_sfdp_param(ctx, 0x04);
|
||||
flash->size = (flash_bits >> 3) + 1;
|
||||
|
||||
memcpy(&flash->spi, dev, sizeof(*dev));
|
||||
flash->name = "Apollolake hardware sequencer";
|
||||
|
||||
/* Can erase both 4 KiB and 64 KiB chunks. Declare the smaller size. */
|
||||
flash->sector_size = 4 * KiB;
|
||||
/*
|
||||
* FIXME: Get erase+cmd, and status_cmd from SFDP.
|
||||
*
|
||||
* flash->erase_cmd = ???
|
||||
* flash->status_cmd = ???
|
||||
*/
|
||||
|
||||
flash->internal_write = nuclear_spi_flash_write;
|
||||
flash->internal_erase = nuclear_spi_flash_erase;
|
||||
flash->internal_read = nuclear_spi_flash_read;
|
||||
flash->internal_status = nuclear_spi_flash_status;
|
||||
|
||||
return flash;
|
||||
}
|
||||
|
||||
int spi_flash_get_fpr_info(struct fpr_info *info)
|
||||
{
|
||||
BOILERPLATE_CREATE_CTX(ctx);
|
||||
|
||||
if (!ctx->mmio_base)
|
||||
return -1;
|
||||
|
||||
info->base = ctx->mmio_base + SPIBAR_FPR_BASE;
|
||||
info->max = SPIBAR_FPR_MAX;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -1,94 +0,0 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2016 Intel Corp.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef _SOC_APOLLOLAKE_SPI_H_
|
||||
#define _SOC_APOLLOLAKE_SPI_H_
|
||||
|
||||
/* PCI configuration registers */
|
||||
#define SPIBAR_BIOS_CONTROL 0xdc
|
||||
/* Bit definitions for BIOS_CONTROL */
|
||||
#define SPIBAR_BIOS_CONTROL_WPD (1 << 0)
|
||||
#define SPIBAR_BIOS_CONTROL_CACHE_DISABLE (1 << 2)
|
||||
#define SPIBAR_BIOS_CONTROL_PREFETCH_ENABLE (1 << 3)
|
||||
#define SPIBAR_BIOS_CONTROL_EISS (1 << 5)
|
||||
|
||||
/* Maximum bytes of data that can fit in FDATAn registers */
|
||||
#define SPIBAR_FDATA_FIFO_SIZE 0x40
|
||||
|
||||
/* Register offsets from the MMIO region base (PCI_BASE_ADDRESS_0) */
|
||||
#define SPIBAR_BIOS_BFPREG 0x00
|
||||
#define SPIBAR_HSFSTS_CTL 0x04
|
||||
#define SPIBAR_FADDR 0x08
|
||||
#define SPIBAR_FDATA(n) (0x10 + ((n) & 0xf) * 4)
|
||||
#define SPIBAR_FPR_BASE 0x84
|
||||
#define SPIBAR_PTINX 0xcc
|
||||
#define SPIBAR_PTDATA 0xd0
|
||||
|
||||
#define SPIBAR_FPR_MAX 5
|
||||
|
||||
/* Bit definitions and masks for BIOS_BFPREG register. */
|
||||
#define SPIBAR_BFPREG_PRB_MASK (0x7fff)
|
||||
#define SPIBAR_BFPREG_PRL_SHIFT (16)
|
||||
#define SPIBAR_BFPREG_PRL_MASK (0x7fff << SPIBAR_BFPREG_PRL_SHIFT)
|
||||
#define SPIBAR_BFPREG_SBRS (1 << 31)
|
||||
|
||||
/* Bit definitions for HSFSTS_CTL register */
|
||||
#define SPIBAR_HSFSTS_FBDC_MASK (0x3f << 24)
|
||||
#define SPIBAR_HSFSTS_FBDC(n) (((n) << 24) & SPIBAR_HSFSTS_FBDC_MASK)
|
||||
#define SPIBAR_HSFSTS_WET (1 << 21)
|
||||
#define SPIBAR_HSFSTS_FCYCLE_MASK (0xf << 17)
|
||||
#define SPIBAR_HSFSTS_FCYCLE(cyc) (((cyc) << 17) \
|
||||
& SPIBAR_HSFSTS_FCYCLE_MASK)
|
||||
#define SPIBAR_HSFSTS_FGO (1 << 16)
|
||||
#define SPIBAR_HSFSTS_FLOCKDN (1 << 15)
|
||||
#define SPIBAR_HSFSTS_FDV (1 << 14)
|
||||
#define SPIBAR_HSFSTS_FDOPSS (1 << 13)
|
||||
#define SPIBAR_HSFSTS_SAF_CE (1 << 8)
|
||||
#define SPIBAR_HSFSTS_SAF_ACTIVE (1 << 7)
|
||||
#define SPIBAR_HSFSTS_SAF_LE (1 << 6)
|
||||
#define SPIBAR_HSFSTS_SCIP (1 << 5)
|
||||
#define SPIBAR_HSFSTS_SAF_DLE (1 << 4)
|
||||
#define SPIBAR_HSFSTS_SAF_ERROR (1 << 3)
|
||||
#define SPIBAR_HSFSTS_AEL (1 << 2)
|
||||
#define SPIBAR_HSFSTS_FCERR (1 << 1)
|
||||
#define SPIBAR_HSFSTS_FDONE (1 << 0)
|
||||
#define SPIBAR_HSFSTS_W1C_BITS (0xff)
|
||||
/* Supported flash cycle types */
|
||||
#define SPIBAR_HSFSTS_CYCLE_READ SPIBAR_HSFSTS_FCYCLE(0)
|
||||
#define SPIBAR_HSFSTS_CYCLE_WRITE SPIBAR_HSFSTS_FCYCLE(2)
|
||||
#define SPIBAR_HSFSTS_CYCLE_4K_ERASE SPIBAR_HSFSTS_FCYCLE(3)
|
||||
#define SPIBAR_HSFSTS_CYCLE_64K_ERASE SPIBAR_HSFSTS_FCYCLE(4)
|
||||
#define SPIBAR_HSFSTS_CYCLE_RD_STATUS SPIBAR_HSFSTS_FCYCLE(8)
|
||||
|
||||
/* Bit definitions for PTINX register */
|
||||
#define SPIBAR_PTINX_COMP_0 (0 << 14)
|
||||
#define SPIBAR_PTINX_COMP_1 (1 << 14)
|
||||
#define SPIBAR_PTINX_HORD_SFDP (0 << 12)
|
||||
#define SPIBAR_PTINX_HORD_PARAM (1 << 12)
|
||||
#define SPIBAR_PTINX_HORD_JEDEC (2 << 12)
|
||||
#define SPIBAR_PTINX_IDX_MASK 0xffc
|
||||
|
||||
/*
|
||||
* Reads status register. On success returns 0 and status contains the value
|
||||
* read from the status register. On error returns -1.
|
||||
*/
|
||||
int spi_flash_read_status(uint8_t *status);
|
||||
|
||||
/* Read SPI controller register. */
|
||||
uint32_t spi_flash_ctrlr_reg_read(uint16_t reg);
|
||||
|
||||
void spi_flash_init(void);
|
||||
#endif
|
||||
|
|
@ -22,7 +22,7 @@
|
|||
#include <commonlib/region.h>
|
||||
#include <console/console.h>
|
||||
#include <fmap.h>
|
||||
#include <soc/flash_ctrlr.h>
|
||||
#include <intelblocks/fast_spi.h>
|
||||
#include <soc/mmap_boot.h>
|
||||
|
||||
/*
|
||||
|
|
@ -65,7 +65,7 @@ static struct xlate_region_device real_dev CAR_GLOBAL;
|
|||
|
||||
static void bios_mmap_init(void)
|
||||
{
|
||||
size_t size, start, bios_end, bios_mapped_size;
|
||||
size_t size, start, bios_mapped_size;
|
||||
uintptr_t base;
|
||||
|
||||
size = car_get_var(bios_size);
|
||||
|
|
@ -73,18 +73,7 @@ static void bios_mmap_init(void)
|
|||
/* If bios_size is initialized, then bail out. */
|
||||
if (size != 0)
|
||||
return;
|
||||
|
||||
/*
|
||||
* BIOS_BFPREG provides info about BIOS Flash Primary Region
|
||||
* Base and Limit.
|
||||
* Base and Limit fields are in units of 4KiB.
|
||||
*/
|
||||
uint32_t val = spi_flash_ctrlr_reg_read(SPIBAR_BIOS_BFPREG);
|
||||
|
||||
start = (val & SPIBAR_BFPREG_PRB_MASK) * 4 * KiB;
|
||||
bios_end = (((val & SPIBAR_BFPREG_PRL_MASK) >>
|
||||
SPIBAR_BFPREG_PRL_SHIFT) + 1) * 4 * KiB;
|
||||
size = bios_end - start;
|
||||
start = fast_spi_get_bios_region(&size);
|
||||
|
||||
/* BIOS region is mapped right below 4G. */
|
||||
base = 4ULL * GiB - size;
|
||||
|
|
|
|||
|
|
@ -33,7 +33,6 @@
|
|||
#include <fsp/util.h>
|
||||
#include <reset.h>
|
||||
#include <soc/cpu.h>
|
||||
#include <soc/flash_ctrlr.h>
|
||||
#include <soc/intel/common/mrc_cache.h>
|
||||
#include <soc/iomap.h>
|
||||
#include <soc/systemagent.h>
|
||||
|
|
|
|||
Loading…
Reference in New Issue