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soc/amd/stoneyridge: unify and align include guards with picasso 

Change-Id: I0cc06e33ed5c9b9bd97ed1f10f9c2d8019b1b5ac
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47582
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Felix Held 2020-11-14 00:39:45 +01:00
parent 4feef09c65
commit e70c32f7b7
11 changed files with 33 additions and 33 deletions
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6
src/soc/amd/stoneyridge/include/soc/acpi.h
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@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#ifndef __SOC_STONEYRIDGE_ACPI_H__
#define __SOC_STONEYRIDGE_ACPI_H__
#ifndef AMD_STONEYRIDGE_ACPI_H
#define AMD_STONEYRIDGE_ACPI_H
#include <acpi/acpi.h>
@ -16,4 +16,4 @@ unsigned long southbridge_write_acpi_tables(const struct device *device,
const char *soc_acpi_name(const struct device *dev);
#endif /* __SOC_STONEYRIDGE_ACPI_H__ */
#endif /* AMD_STONEYRIDGE_ACPI_H */

6
src/soc/amd/stoneyridge/include/soc/amd_pci_int_defs.h
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@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef __AMD_PCI_INT_DEFS_H__
#define __AMD_PCI_INT_DEFS_H__
#ifndef AMD_STONEYRIDGE_AMD_PCI_INT_DEFS_H
#define AMD_STONEYRIDGE_AMD_PCI_INT_DEFS_H
/*
* PIRQ and device routing - these define the index into the
@ -44,4 +44,4 @@
#define PIRQ_UART0 0x74
#define PIRQ_UART1 0x75
#endif /* __AMD_PCI_INT_DEFS_H__ */
#endif /* AMD_STONEYRIDGE_AMD_PCI_INT_DEFS_H */

6
src/soc/amd/stoneyridge/include/soc/cpu.h
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@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef __STONEYRIDGE_CPU_H__
#define __STONEYRIDGE_CPU_H__
#ifndef AMD_STONEYRIDGE_CPU_H
#define AMD_STONEYRIDGE_CPU_H
/*
* Set a variable MTRR in bootblock and/or romstage. AGESA will use the lowest
@ -16,4 +16,4 @@
void check_mca(void);
#endif /* __STONEYRIDGE_CPU_H__ */
#endif /* AMD_STONEYRIDGE_CPU_H */

6
src/soc/amd/stoneyridge/include/soc/gpio.h
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@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef __STONEYRIDGE_GPIO_H__
#define __STONEYRIDGE_GPIO_H__
#ifndef AMD_STONEYRIDGE_GPIO_H
#define AMD_STONEYRIDGE_GPIO_H
#define GPIO_DEVICE_NAME "AMD0030"
#define GPIO_DEVICE_DESC "GPIO Controller"
@ -292,4 +292,4 @@
#define GPIO_2_EVENT GEVENT_8
#endif /* __ACPI__ */
#endif /* __STONEYRIDGE_GPIO_H__ */
#endif /* AMD_STONEYRIDGE_GPIO_H */

6
src/soc/amd/stoneyridge/include/soc/i2c.h
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@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef __STONEYRIDGE_I2C_H__
#define __STONEYRIDGE_I2C_H__
#ifndef AMD_STONEYRIDGE_I2C_H
#define AMD_STONEYRIDGE_I2C_H
#include <types.h>
#include <soc/gpio.h>
@ -29,4 +29,4 @@ struct soc_amd_i2c_save {
void sb_reset_i2c_slaves(void);
#endif /* __STONEYRIDGE_I2C_H__ */
#endif /* AMD_STONEYRIDGE_I2C_H */

6
src/soc/amd/stoneyridge/include/soc/iomap.h
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@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef __SOC_STONEYRIDGE_IOMAP_H__
#define __SOC_STONEYRIDGE_IOMAP_H__
#ifndef AMD_STONEYRIDGE_IOMAP_H
#define AMD_STONEYRIDGE_IOMAP_H
/* MMIO Ranges */
#define PSP_MAILBOX_BAR3_BASE 0xf0a00000
@ -51,4 +51,4 @@
#define BIOSRAM_UMA_SIZE 0xf4 /* 4 bytes */
#define BIOSRAM_UMA_BASE 0xf8 /* 8 bytes */
#endif /* __SOC_STONEYRIDGE_IOMAP_H__ */
#endif /* AMD_STONEYRIDGE_IOMAP_H */

6
src/soc/amd/stoneyridge/include/soc/northbridge.h
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@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef __PI_STONEYRIDGE_NORTHBRIDGE_H__
#define __PI_STONEYRIDGE_NORTHBRIDGE_H__
#ifndef AMD_STONEYRIDGE_NORTHBRIDGE_H
#define AMD_STONEYRIDGE_NORTHBRIDGE_H
#include <device/device.h>
#include <types.h>
@ -89,4 +89,4 @@ void fam15_finalize(void *chip_info);
void set_warm_reset_flag(void);
int is_warm_reset(void);
#endif /* __PI_STONEYRIDGE_NORTHBRIDGE_H__ */
#endif /* AMD_STONEYRIDGE_NORTHBRIDGE_H */

6
src/soc/amd/stoneyridge/include/soc/pci_devs.h
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@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef __PI_STONEYRIDGE_PCI_DEVS_H__
#define __PI_STONEYRIDGE_PCI_DEVS_H__
#ifndef AMD_STONEYRIDGE_PCI_DEVS_H
#define AMD_STONEYRIDGE_PCI_DEVS_H
#include <device/pci_def.h>
#include <amdblocks/pci_devs.h>
@ -201,4 +201,4 @@
#define SD_DEVFN PCI_DEVFN(SD_DEV, SD_FUNC)
#define SOC_SD_DEV _SOC_DEV(SD_DEV, SD_FUNC)
#endif /* __PI_STONEYRIDGE_PCI_DEVS_H__ */
#endif /* AMD_STONEYRIDGE_PCI_DEVS_H */

6
src/soc/amd/stoneyridge/include/soc/romstage.h
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@ -1,8 +1,8 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef __STONEYRIDGE_ROMSTAGE_H__
#define __STONEYRIDGE_ROMSTAGE_H__
#ifndef AMD_STONEYRIDGE_ROMSTAGE_H
#define AMD_STONEYRIDGE_ROMSTAGE_H
void mainboard_romstage_entry_s3(int s3_resume);
#endif /* __STONEYRIDGE_ROMSTAGE_H__ */
#endif /* AMD_STONEYRIDGE_ROMSTAGE_H */

6
src/soc/amd/stoneyridge/include/soc/smi.h
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@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#ifndef __SOUTHBRIDGE_AMD_PI_STONEYRIDGE_SMI_H__
#define __SOUTHBRIDGE_AMD_PI_STONEYRIDGE_SMI_H__
#ifndef AMD_STONEYRIDGE_SMI_H
#define AMD_STONEYRIDGE_SMI_H
#define SMI_GEVENTS 24
#define SCIMAPS 58
@ -218,4 +218,4 @@ void disable_gevent_smi(uint8_t gevent);
void gpe_configure_sci(const struct sci_source *scis, size_t num_gpes);
void soc_route_sci(uint8_t event);
#endif /* __SOUTHBRIDGE_AMD_PI_STONEYRIDGE_SMI_H__ */
#endif /* AMD_STONEYRIDGE_SMI_H */

6
src/soc/amd/stoneyridge/include/soc/southbridge.h
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@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef __STONEYRIDGE_H__
#define __STONEYRIDGE_H__
#ifndef AMD_STONEYRIDGE_SOUTHBRIDGE_H
#define AMD_STONEYRIDGE_SOUTHBRIDGE_H
#include <types.h>
#include <device/device.h>
@ -349,4 +349,4 @@ void i2c_soc_early_init(void);
/* Initialize all the i2c buses that are not marked with early init. */
void i2c_soc_init(void);
#endif /* __STONEYRIDGE_H__ */
#endif /* AMD_STONEYRIDGE_SOUTHBRIDGE_H */