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mb/google/dedede: Clean up LTE device enabling 

On some dedede variants, USB port 2.3/3.3 might be connected to either
LTE device or Type-A external port depending upon FW_CONFIG. Commit
856b579 ("mb/google/dedede/var/kracko: Update LTE USB port
configuration") enabled Type-A external port by default in override
tree and updated the config dynamically for LTE USB device if
FW_CONFIG indicated support for it. This was required because sconfig
lacked the support for multiple override devices. Commit
b9c22e0 ("util/sconfig: Compare probe conditions for override device
match") fixed this behavior in sconfig and now we can add multiple
override devices using different FW_CONFIG probe statements in
override tree. Hence, this change moves the LTE USB device to override
tree for metaknight, kracko and drawcia variants.

In addition to that, drawcia needs to be update reset_gpio depending
upon board_id. Thus, alias `lte_usb2` is used in drawcia override tree
to fix the reset_gpio for older boards i.e. board_id <= 9.

Change-Id: Ie5b205594680d9c2b8543c5c99325d95620cafd2
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57742
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
This commit is contained in:
Furquan Shaikh 2021-09-16 19:58:20 -07:00
parent 2cf88c185a
commit e7821e8de0
11 changed files with 84 additions and 96 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
src/mainboard/google/dedede/variants/baseboard/Makefile.inc
View File

@ -3,6 +3,5 @@ bootblock-y += gpio.c
romstage-y += memory.c
ramstage-y += gpio.c
ramstage-y += ramstage.c
smm-y += gpio.c

48
src/mainboard/google/dedede/variants/baseboard/ramstage.c
View File

@ -1,48 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#include <acpi/acpi_device.h>
#include <baseboard/variants.h>
#include <console/console.h>
#include <drivers/usb/acpi/chip.h>
#include <fw_config.h>
#include <gpio.h>
#include <soc/pci_devs.h>
#define LTE_USB_PORT_ID 3
#define LTE_USB_PORT_TYPE 2
void update_lte_device(struct acpi_gpio *lte_reset_gpio, struct acpi_gpio *lte_enable_gpio)
{
struct device *xhci, *hub = NULL, *port = NULL;
struct drivers_usb_acpi_config *config;
xhci = pcidev_path_on_root(PCH_DEVFN_XHCI);
if (!xhci) {
printk(BIOS_ERR, "%s: Could not locate XHCI device in DT\n", __func__);
return;
}
while ((hub = dev_bus_each_child(xhci->link_list, hub)) != NULL) {
while ((port = dev_bus_each_child(hub->link_list, port)) != NULL) {
if (!port->chip_info || port->path.usb.port_id != LTE_USB_PORT_ID)
continue;
if (fw_config_probe(FW_CONFIG(DB_PORTS, DB_PORTS_LTE_HDMI)) ||
fw_config_probe(FW_CONFIG(DB_PORTS, DB_PORTS_1C_LTE)) ||
fw_config_probe(FW_CONFIG(DB_PORTS, DB_PORTS_1A_HDMI_LTE))) {
config = port->chip_info;
config->type = UPC_TYPE_INTERNAL;
if (port->path.usb.port_type == LTE_USB_PORT_TYPE) {
config->has_power_resource = 1;
memcpy(&config->reset_gpio, lte_reset_gpio,
sizeof(config->reset_gpio));
config->reset_off_delay_ms = 20;
memcpy(&config->enable_gpio, lte_enable_gpio,
sizeof(config->enable_gpio));
config->enable_delay_ms = 20;
}
}
}
}
}

2
src/mainboard/google/dedede/variants/boten/overridetree.cb
View File

@ -151,7 +151,7 @@ chip soc/intel/jasperlake
register "reset_off_delay_ms" = "10"
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A10)"
register "enable_delay_ms" = "20"
device usb 2.3 on end
device usb 2.3 alias usb2_lte on end
end
chip drivers/usb/acpi
register "desc" = ""UFCamera""

27
src/mainboard/google/dedede/variants/drawcia/overridetree.cb
View File

@ -151,13 +151,25 @@ chip soc/intel/jasperlake
chip drivers/usb/acpi
device usb 0.0 on
chip drivers/usb/acpi
register "desc" = ""Multi-use Port""
register "desc" = ""LTE""
register "type" = "UPC_TYPE_INTERNAL"
register "group" = "ACPI_PLD_GROUP(2, 2)"
register "has_power_resource" = "1"
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H17)"
register "reset_off_delay_ms" = "20"
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A10)"
register "enable_delay_ms" = "20"
device usb 2.3 alias lte_usb2 on
probe DB_PORTS DB_PORTS_1A_HDMI_LTE
end
end
chip drivers/usb/acpi
register "desc" = ""Right Type-A Port""
register "type" = "UPC_TYPE_A"
register "group" = "ACPI_PLD_GROUP(2, 2)"
device usb 2.3 on
probe DB_PORTS DB_PORTS_1A_HDMI
probe DB_PORTS DB_PORTS_1C_1A
probe DB_PORTS DB_PORTS_1A_HDMI_LTE
end
end
chip drivers/usb/acpi
@ -166,13 +178,20 @@ chip soc/intel/jasperlake
device usb 2.5 on end
end
chip drivers/usb/acpi
register "desc" = ""Multi-use Port""
register "desc" = ""LTE""
register "type" = "UPC_TYPE_INTERNAL"
register "group" = "ACPI_PLD_GROUP(2, 2)"
device usb 3.3 on
probe DB_PORTS DB_PORTS_1A_HDMI_LTE
end
end
chip drivers/usb/acpi
register "desc" = ""Right Type-A Port""
register "type" = "UPC_TYPE_USB3_A"
register "group" = "ACPI_PLD_GROUP(2, 2)"
device usb 3.3 on
probe DB_PORTS DB_PORTS_1A_HDMI
probe DB_PORTS DB_PORTS_1C_1A
probe DB_PORTS DB_PORTS_1A_HDMI_LTE
end
end
end

24
src/mainboard/google/dedede/variants/drawcia/ramstage.c
View File

@ -2,19 +2,23 @@
#include <baseboard/variants.h>
#include <boardid.h>
static struct acpi_gpio lte_reset_gpio = ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H0);
static struct acpi_gpio lte_enable_gpio = ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A10);
/* New lte reset for drapwer DVT*/
static struct acpi_gpio lte_new_reset_gpio = ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H17);
#include <device/device.h>
#include <drivers/usb/acpi/chip.h>
void variant_devtree_update(void)
{
uint32_t board_version = board_id();
struct device *lte_usb2 = DEV_PTR(lte_usb2);
struct drivers_usb_acpi_config *config;
struct acpi_gpio lte_reset_gpio = ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H0);
if (board_version <= 9) /* board version 9 is drawper EVT */
update_lte_device(&lte_reset_gpio, &lte_enable_gpio);
else
update_lte_device(&lte_new_reset_gpio, &lte_enable_gpio);
/* board version 9 is drawper EVT */
if (board_version > 9)
return;
if (lte_usb2 == NULL)
return;
config = config_of(lte_usb2);
config->reset_gpio = lte_reset_gpio;
}

1
src/mainboard/google/dedede/variants/kracko/Makefile.inc
View File

@ -1,6 +1,5 @@
## SPDX-License-Identifier: GPL-2.0-or-later
ramstage-y += gpio.c
ramstage-y += ramstage.c
smm-y += variant.c

27
src/mainboard/google/dedede/variants/kracko/overridetree.cb
View File

@ -63,11 +63,23 @@ chip soc/intel/jasperlake
chip drivers/usb/acpi
device usb 0.0 on
chip drivers/usb/acpi
register "desc" = ""Multi-use Port""
register "desc" = ""LTE""
register "type" = "UPC_TYPE_INTERNAL"
register "group" = "ACPI_PLD_GROUP(2, 2)"
register "has_power_resource" = "1"
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H17)"
register "reset_off_delay_ms" = "20"
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A10)"
register "enable_delay_ms" = "20"
device usb 2.3 on
probe DB_PORTS DB_PORTS_1C_LTE
end
end
chip drivers/usb/acpi
register "desc" = ""Right Type-A Port""
register "type" = "UPC_TYPE_A"
register "group" = "ACPI_PLD_GROUP(2, 2)"
device usb 2.3 on
probe DB_PORTS DB_PORTS_1C_LTE
probe DB_PORTS DB_PORTS_1C_1A
end
end
@ -82,11 +94,18 @@ chip soc/intel/jasperlake
device usb 2.6 on end
end
chip drivers/usb/acpi
register "desc" = ""Multi-use Port""
register "type" = "UPC_TYPE_USB3_A"
register "desc" = ""LTE""
register "type" = "UPC_TYPE_INTERNAL"
register "group" = "ACPI_PLD_GROUP(2, 2)"
device usb 3.3 on
probe DB_PORTS DB_PORTS_1C_LTE
end
end
chip drivers/usb/acpi
register "desc" = ""Right Type-A Port""
register "type" = "UPC_TYPE_USB3_A"
register "group" = "ACPI_PLD_GROUP(2, 2)"
device usb 3.3 on
probe DB_PORTS DB_PORTS_1C_1A
end
end

11
src/mainboard/google/dedede/variants/kracko/ramstage.c
View File

@ -1,11 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#include <baseboard/variants.h>
static struct acpi_gpio lte_reset_gpio = ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H17);
static struct acpi_gpio lte_enable_gpio = ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A10);
void variant_devtree_update(void)
{
update_lte_device(&lte_reset_gpio, &lte_enable_gpio);
}

1
src/mainboard/google/dedede/variants/metaknight/Makefile.inc
View File

@ -1,6 +1,5 @@
# SPDX-License-Identifier: GPL-2.0-only
ramstage-y += gpio.c
ramstage-y += ramstage.c
smm-y += variant.c

27
src/mainboard/google/dedede/variants/metaknight/overridetree.cb
View File

@ -109,12 +109,24 @@ chip soc/intel/jasperlake
chip drivers/usb/acpi
device usb 0.0 on
chip drivers/usb/acpi
register "desc" = ""Multi-use Port""
register "desc" = ""LTE""
register "type" = "UPC_TYPE_INTERNAL"
register "group" = "ACPI_PLD_GROUP(2, 2)"
register "has_power_resource" = "1"
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H17)"
register "reset_off_delay_ms" = "20"
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A10)"
register "enable_delay_ms" = "20"
device usb 2.3 on
probe DB_PORTS DB_PORTS_LTE_HDMI
end
end
chip drivers/usb/acpi
register "desc" = ""Right Type-A Port""
register "type" = "UPC_TYPE_A"
register "group" = "ACPI_PLD_GROUP(2, 2)"
device usb 2.3 on
probe DB_PORTS DB_PORTS_1A_HDMI
probe DB_PORTS DB_PORTS_LTE_HDMI
end
end
chip drivers/usb/acpi
@ -128,12 +140,19 @@ chip soc/intel/jasperlake
device usb 2.6 on end
end
chip drivers/usb/acpi
register "desc" = ""Multi-use Port""
register "desc" = ""LTE""
register "type" = "UPC_TYPE_INTERNAL"
register "group" = "ACPI_PLD_GROUP(2, 2)"
device usb 3.3 on
probe DB_PORTS DB_PORTS_LTE_HDMI
end
end
chip drivers/usb/acpi
register "desc" = ""Right Type-A Port""
register "type" = "UPC_TYPE_USB3_A"
register "group" = "ACPI_PLD_GROUP(2, 2)"
device usb 3.3 on
probe DB_PORTS DB_PORTS_1A_HDMI
probe DB_PORTS DB_PORTS_LTE_HDMI
end
end
end

11
src/mainboard/google/dedede/variants/metaknight/ramstage.c
View File

@ -1,11 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#include <baseboard/variants.h>
static struct acpi_gpio lte_reset_gpio = ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H17);
static struct acpi_gpio lte_enable_gpio = ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A10);
void variant_devtree_update(void)
{
update_lte_device(&lte_reset_gpio, &lte_enable_gpio);
}