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google/reef: Update EMMC DLL setting in all mode 

Update tuned DLL setting on all other mode, including SDR12
SDR25 and DDR50.

Change-Id: I1eb85ac6080fd78f63816d3fa9ef482484bd9f94
Signed-off-by: Zhao, Lijian <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/15210
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Zhao, Lijian 2016-06-15 17:22:08 -07:00 committed by Aaron Durbin
parent fda691ef53
commit e813c15443
1 changed files with 12 additions and 12 deletions
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24
src/mainboard/google/reef/devicetree.cb
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@ -12,24 +12,24 @@ chip soc/intel/apollolake
register "emmc_tx_data_cntl1" = "0x0C11" # HS400 required register "emmc_tx_data_cntl1" = "0x0C11" # HS400 required
# EMMC TX DATA Delay 2# # EMMC TX DATA Delay 2#
# 0x1C[30:24] stands for 28*125 = 3500 pSec delay for SDR50 # 0x00[30:24] stands for 0*125 = no delay for SDR50
# 0x1C[22:16] stands for 28*125 = 3500 pSec delay for DDR50 # 0x2B[22:16] stands for 43*125 = 5375 pSec delay for DDR50
# 0x1C[14:8] stands for 28*125 = 3500 pSec delay for SDR25/HS50 # 0x29[14:8] stands for 41*125 = 5125 pSec delay for SDR25/HS50
# 0x00[6:0] stands for 0 delay for SDR12/Compatibility mode # 0x29[6:0] stands for 41*125 = 5125 pSec delay for SDR12
register "emmc_tx_data_cntl2" = "0x1c1c1c00" register "emmc_tx_data_cntl2" = "0x002B2929"
# EMMC RX CMD/DATA Delay 1# # EMMC RX CMD/DATA Delay 1#
# 0x1C[30:24] stands for 28*125 = 3500 pSec delay for SDR50 # 0x00[30:24] stands for 0*125 = no delay for SDR50
# 0x1C[22:16] stands for 28*125 = 3500 pSec delay for DDR50 # 0x12[22:16] stands for 18*125 = 2250 pSec delay for DDR50
# 0x1C[14:8] stands for 28*125 = 3500 pSec delay for SDR25/HS50 # 0x57[14:8] stands for 87*125 = 10875 pSec delay for SDR25/HS50
# 0x00[6:0] stands for 0 delay for SDR12/Compatibility # 0x3B[6:0] stands for 59*125= 7375 pSec delay for SDR12
register "emmc_rx_cmd_data_cntl1" = "0x1c1c1c00" register "emmc_rx_cmd_data_cntl1" = "0x0012573B"
# EMMC RX CMD/DATA Delay 2# # EMMC RX CMD/DATA Delay 2#
# 0x01[17:16] stands for Rx Clock before Output Buffer # 0x01[17:16] stands for Rx Clock before Output Buffer
# 0x00[14:8] stands for 0 delay for Auto Tuning Mode # 0x00[14:8] stands for 0 delay for Auto Tuning Mode
# 0x1C[6:0] stands for 28*125 = 3500 pSec delay for SDR104/HS200 # 0x1C[6:0] stands for 28*125 = 3500 pSec delay for HS200
register "emmc_rx_cmd_data_cntl2" = "0x1001c" register "emmc_rx_cmd_data_cntl2" = "0x1001C"
device domain 0 on device domain 0 on
device pci 00.0 on end # - Host Bridge device pci 00.0 on end # - Host Bridge