Remove Dell s1850
It's almost 10 years old. It never worked. It's a soldered in FLASH, so mistakes are fatal. It's got no redeeming features. Remove the dell directory. In 12 years of trying to work with Dell we have not had much interest. It's misleading to have it there. Change-Id: I83ff009bd7a6d5289229ca39608789ae5c33710b Reviewed-on: http://review.coreboot.org/876 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Ron Minnich
Stefan Reinauer
parent
d3801f4f6f
commit
e875328c79
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@ -44,8 +44,6 @@ config VENDOR_BROADCOM
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bool "Broadcom"
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config VENDOR_COMPAQ
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bool "Compaq"
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config VENDOR_DELL
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bool "Dell"
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config VENDOR_DIGITALLOGIC
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bool "DIGITAL-LOGIC"
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config VENDOR_EAGLELION
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@ -149,7 +147,6 @@ source "src/mainboard/bifferos/Kconfig"
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source "src/mainboard/biostar/Kconfig"
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source "src/mainboard/broadcom/Kconfig"
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source "src/mainboard/compaq/Kconfig"
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source "src/mainboard/dell/Kconfig"
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source "src/mainboard/digitallogic/Kconfig"
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source "src/mainboard/eaglelion/Kconfig"
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source "src/mainboard/ecs/Kconfig"
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@ -1,17 +0,0 @@
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if VENDOR_DELL
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choice
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prompt "Mainboard model"
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config BOARD_DELL_S1850
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bool "PowerEdge 1850"
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endchoice
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source "src/mainboard/dell/s1850/Kconfig"
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config MAINBOARD_VENDOR
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string
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default "Dell"
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endif # VENDOR_DELL
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@ -1,44 +0,0 @@
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if BOARD_DELL_S1850
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config BOARD_SPECIFIC_OPTIONS # dummy
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def_bool y
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select ARCH_X86
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select CPU_INTEL_SOCKET_MPGA604
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select NORTHBRIDGE_INTEL_E7520
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select SOUTHBRIDGE_INTEL_I82801EX
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select SOUTHBRIDGE_INTEL_PXHD
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select SUPERIO_NSC_PC8374
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select ROMCC
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select HAVE_OPTION_TABLE
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select BOARD_HAS_HARD_RESET
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select HAVE_PIRQ_TABLE
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select HAVE_MP_TABLE
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select USE_WATCHDOG_ON_BOOT
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select BOARD_ROMSIZE_KB_1024
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select UDELAY_TSC
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config MAINBOARD_DIR
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string
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default dell/s1850
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config MAINBOARD_PART_NUMBER
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string
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default "PowerEdge 1850"
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config MAX_CPUS
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int
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default 4
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config MAX_PHYSICAL_CPUS
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int
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default 1
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config IRQ_SLOT_COUNT
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int
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default 9
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config DIMM_MAP_LOGICAL
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hex
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default 0x2841
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endif # BOARD_DELL_S1850
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@ -1 +0,0 @@
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ROMCCFLAGS := -mcpu=p4 -O2
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@ -1,3 +0,0 @@
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extern struct chip_operations mainboard_ops;
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struct mainboard_config {};
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@ -1,80 +0,0 @@
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entries
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#start-bit length config config-ID name
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#0 8 r 0 seconds
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#8 8 r 0 alarm_seconds
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#16 8 r 0 minutes
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#24 8 r 0 alarm_minutes
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#32 8 r 0 hours
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#40 8 r 0 alarm_hours
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#48 8 r 0 day_of_week
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#56 8 r 0 day_of_month
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#64 8 r 0 month
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#72 8 r 0 year
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#80 4 r 0 rate_select
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#84 3 r 0 REF_Clock
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#87 1 r 0 UIP
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#88 1 r 0 auto_switch_DST
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#89 1 r 0 24_hour_mode
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#90 1 r 0 binary_values_enable
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#91 1 r 0 square-wave_out_enable
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#92 1 r 0 update_finished_enable
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#93 1 r 0 alarm_interrupt_enable
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#94 1 r 0 periodic_interrupt_enable
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#95 1 r 0 disable_clock_updates
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#96 288 r 0 temporary_filler
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0 384 r 0 reserved_memory
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384 1 e 4 boot_option
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385 1 e 4 last_boot
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386 1 e 1 ECC_memory
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388 4 r 0 reboot_bits
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392 3 e 5 baud_rate
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395 1 e 2 hyper_threading
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400 1 e 1 power_on_after_fail
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412 4 e 6 debug_level
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416 4 e 7 boot_first
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420 4 e 7 boot_second
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424 4 e 7 boot_third
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428 4 h 0 boot_index
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432 8 h 0 boot_countdown
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728 256 h 0 user_data
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984 16 h 0 check_sum
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# Reserve the extended AMD configuration registers
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1000 24 r 0 amd_reserved
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enumerations
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#ID value text
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1 0 Disable
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1 1 Enable
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2 0 Enable
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2 1 Disable
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4 0 Fallback
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4 1 Normal
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5 0 115200
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5 1 57600
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5 2 38400
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5 3 19200
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5 4 9600
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5 5 4800
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5 6 2400
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5 7 1200
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6 6 Notice
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6 7 Info
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6 8 Debug
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6 9 Spew
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7 0 Network
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7 1 HDD
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7 2 Floppy
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7 8 Fallback_Network
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7 9 Fallback_HDD
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7 10 Fallback_Floppy
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#7 3 ROM
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checksums
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checksum 392 983 984
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@ -1,289 +0,0 @@
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#include <spd.h>
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static void print_reg(unsigned char index)
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{
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unsigned char data;
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outb(index, 0x2e);
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data = inb(0x2f);
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print_debug("0x");
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print_debug_hex8(index);
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print_debug(": 0x");
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print_debug_hex8(data);
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print_debug("\n");
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return;
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}
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static void xbus_en(void)
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{
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/* select the XBUS function in the SIO */
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outb(0x07, 0x2e);
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outb(0x0f, 0x2f);
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outb(0x30, 0x2e);
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outb(0x01, 0x2f);
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return;
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}
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static void setup_func(unsigned char func)
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{
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/* select the function in the SIO */
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outb(0x07, 0x2e);
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outb(func, 0x2f);
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/* print out the regs */
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print_reg(0x30);
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print_reg(0x60);
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print_reg(0x61);
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print_reg(0x62);
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print_reg(0x63);
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print_reg(0x70);
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print_reg(0x71);
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print_reg(0x74);
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print_reg(0x75);
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return;
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}
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static void siodump(void)
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{
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int i;
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unsigned char data;
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print_debug("\n*** SERVER I/O REGISTERS ***\n");
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for (i=0x10; i<=0x2d; i++) {
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print_reg((unsigned char)i);
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}
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#if 0
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print_debug("\n*** XBUS REGISTERS ***\n");
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setup_func(0x0f);
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for (i=0xf0; i<=0xff; i++) {
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print_reg((unsigned char)i);
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}
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print_debug("\n*** SERIAL 1 CONFIG REGISTERS ***\n");
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setup_func(0x03);
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print_reg(0xf0);
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print_debug("\n*** SERIAL 2 CONFIG REGISTERS ***\n");
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setup_func(0x02);
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print_reg(0xf0);
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#endif
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print_debug("\n*** GPIO REGISTERS ***\n");
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setup_func(0x07);
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for (i=0xf0; i<=0xf8; i++) {
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print_reg((unsigned char)i);
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}
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print_debug("\n*** GPIO VALUES ***\n");
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data = inb(0x68a);
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print_debug("\nGPDO 4: 0x");
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print_debug_hex8(data);
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data = inb(0x68b);
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print_debug("\nGPDI 4: 0x");
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print_debug_hex8(data);
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print_debug("\n");
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#if 0
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print_debug("\n*** WATCHDOG TIMER REGISTERS ***\n");
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setup_func(0x0a);
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print_reg(0xf0);
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print_debug("\n*** FAN CONTROL REGISTERS ***\n");
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setup_func(0x09);
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print_reg(0xf0);
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print_reg(0xf1);
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print_debug("\n*** RTC REGISTERS ***\n");
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setup_func(0x10);
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print_reg(0xf0);
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print_reg(0xf1);
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print_reg(0xf3);
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print_reg(0xf6);
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print_reg(0xf7);
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print_reg(0xfe);
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print_reg(0xff);
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print_debug("\n*** HEALTH MONITORING & CONTROL REGISTERS ***\n");
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setup_func(0x14);
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print_reg(0xf0);
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#endif
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return;
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}
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static void print_debug_pci_dev(unsigned dev)
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{
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print_debug("PCI: ");
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print_debug_hex8((dev >> 16) & 0xff);
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print_debug_char(':');
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print_debug_hex8((dev >> 11) & 0x1f);
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print_debug_char('.');
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print_debug_hex8((dev >> 8) & 7);
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}
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static void print_pci_devices(void)
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{
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device_t dev;
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for(dev = PCI_DEV(0, 0, 0);
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dev <= PCI_DEV(0, 0x1f, 0x7);
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dev += PCI_DEV(0,0,1)) {
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uint32_t id;
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id = pci_read_config32(dev, PCI_VENDOR_ID);
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if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
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(((id >> 16) & 0xffff) == 0xffff) ||
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(((id >> 16) & 0xffff) == 0x0000)) {
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continue;
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}
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print_debug_pci_dev(dev);
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print_debug("\n");
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}
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}
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static void dump_pci_device(unsigned dev)
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{
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int i;
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print_debug_pci_dev(dev);
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print_debug("\n");
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for(i = 0; i <= 255; i++) {
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unsigned char val;
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if ((i & 0x0f) == 0) {
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print_debug_hex8(i);
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print_debug_char(':');
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}
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val = pci_read_config8(dev, i);
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print_debug_char(' ');
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print_debug_hex8(val);
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if ((i & 0x0f) == 0x0f) {
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print_debug("\n");
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}
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}
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}
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static void dump_bar14(unsigned dev)
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{
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int i;
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unsigned long bar;
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print_debug("BAR 14 Dump\n");
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bar = pci_read_config32(dev, 0x14);
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for(i = 0; i <= 0x300; i+=4) {
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#if 0
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unsigned char val;
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if ((i & 0x0f) == 0) {
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print_debug_hex8(i);
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print_debug_char(':');
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}
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val = pci_read_config8(dev, i);
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#endif
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if((i%4)==0) {
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print_debug("\n");
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print_debug_hex16(i);
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print_debug_char(' ');
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}
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print_debug_hex32(read32(bar + i));
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print_debug_char(' ');
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}
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print_debug("\n");
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}
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static void dump_pci_devices(void)
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{
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device_t dev;
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for(dev = PCI_DEV(0, 0, 0);
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dev <= PCI_DEV(0, 0x1f, 0x7);
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dev += PCI_DEV(0,0,1)) {
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uint32_t id;
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id = pci_read_config32(dev, PCI_VENDOR_ID);
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if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
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(((id >> 16) & 0xffff) == 0xffff) ||
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(((id >> 16) & 0xffff) == 0x0000)) {
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continue;
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}
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dump_pci_device(dev);
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}
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}
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void dump_spd_registers(void)
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{
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unsigned device;
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device = DIMM0;
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while(device <= DIMM7) {
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int status = 0;
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int i;
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print_debug("\n");
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print_debug("dimm ");
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print_debug_hex8(device);
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for(i = 0; (i < 256) ; i++) {
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unsigned char byte;
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if ((i % 16) == 0) {
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print_debug("\n");
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print_debug_hex8(i);
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print_debug(": ");
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}
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status = smbus_read_byte(device, i);
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if (status < 0) {
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print_debug("bad device: ");
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print_debug_hex8(-status);
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print_debug("\n");
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break;
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}
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print_debug_hex8(status);
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print_debug_char(' ');
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}
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device++;
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print_debug("\n");
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}
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}
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void show_dram_slots(void)
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{
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unsigned device;
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device = DIMM0;
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while(device <= DIMM7) {
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int status = 0;
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int i;
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print_debug("\n");
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print_debug("dimm ");
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print_debug_hex8(device);
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status = smbus_read_byte(device, 0);
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if (status < 0) {
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print_debug("bad device: ");
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} else {
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print_debug("present: ");
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}
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print_debug_hex8(status);
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print_debug("\n");
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device++;
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print_debug("\n");
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}
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}
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void dump_ipmi_registers(void)
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{
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unsigned device;
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device = 0x42;
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while(device <= 0x42) {
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int status = 0;
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int i;
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print_debug("\n");
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print_debug("ipmi ");
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print_debug_hex8(device);
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for(i = 0; (i < 8) ; i++) {
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unsigned char byte;
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status = smbus_read_byte(device, 2);
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if (status < 0) {
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print_debug("bad device: ");
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print_debug_hex8(-status);
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print_debug("\n");
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break;
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}
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print_debug_hex8(status);
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print_debug_char(' ');
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}
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device++;
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print_debug("\n");
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}
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}
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@ -1,72 +0,0 @@
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chip northbridge/intel/e7520 # mch
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device pci_domain 0 on
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subsystemid 0x15d9 0x5580 inherit
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chip southbridge/intel/i82801ex # i82801er
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# USB ports
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device pci 1d.0 on end
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device pci 1d.1 on end
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device pci 1d.2 on end
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device pci 1d.3 on end
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device pci 1d.7 on end
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# -> Bridge
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device pci 1e.0 on end
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# -> ISA
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device pci 1f.0 on
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chip superio/nsc/pc8374
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device pnp 2e.0 off end
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device pnp 2e.1 off end
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device pnp 2e.2 off end
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device pnp 2e.3 on
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io 0x60 = 0x3f8
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irq 0x70 = 4
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end
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device pnp 2e.4 off end
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device pnp 2e.5 off end
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device pnp 2e.6 off end
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device pnp 2e.7 off end
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device pnp 2e.8 off end
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end
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end
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# -> IDE
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device pci 1f.1 on end
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# -> SATA
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device pci 1f.2 on end
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device pci 1f.3 on end
|
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register "pirq_a_d" = "0x8a07030b"
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register "pirq_e_h" = "0x85808080"
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end
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device pci 00.0 on end
|
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device pci 00.1 on end
|
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device pci 01.0 on end
|
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device pci 02.0 on
|
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chip southbridge/intel/pxhd # pxhd1
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# Bus bridges and ioapics usually bus 1
|
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device pci 0.0 on
|
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# On board gig e1000
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chip drivers/generic/generic
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device pci 03.0 on end
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device pci 03.1 on end
|
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end
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end
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||||
device pci 0.1 on end
|
||||
device pci 0.2 on end
|
||||
device pci 0.3 on end
|
||||
end
|
||||
end
|
||||
device pci 04.0 on end
|
||||
device pci 06.0 on end
|
||||
end
|
||||
device lapic_cluster 0 on
|
||||
chip cpu/intel/socket_mPGA604 # cpu 0
|
||||
device lapic 0 on end
|
||||
end
|
||||
chip cpu/intel/socket_mPGA604 # cpu 1
|
||||
device lapic 6 on end
|
||||
end
|
||||
end
|
||||
register "intrline" = "0x00070100"
|
||||
end
|
||||
|
||||
|
|
@ -1,53 +0,0 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) by the coreboot pirq tool.
|
||||
* This file was programatically generated.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <arch/pirq_routing.h>
|
||||
|
||||
const struct irq_routing_table intel_irq_routing_table = {
|
||||
PIRQ_SIGNATURE,
|
||||
PIRQ_VERSION,
|
||||
32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */
|
||||
0x00, /* Interrupt router bus */
|
||||
(0x11 << 3) | 0x0, /* Interrupt router device */
|
||||
0xc20, /* IRQs devoted exclusively to PCI usage */
|
||||
0x1106, /* Vendor */
|
||||
0x596, /* Device */
|
||||
0, /* Miniport data */
|
||||
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
|
||||
0x66, /* Checksum */
|
||||
{
|
||||
/* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
|
||||
{0x00,(0x14<<3)|0x0, {{0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x01, 0x0deb8}}, 0x1, 0x0},
|
||||
{0x00,(0x0d<<3)|0x0, {{0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x01, 0x0deb8}}, 0x2, 0x0},
|
||||
{0x00,(0x0e<<3)|0x0, {{0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x01, 0xdeb8}, {0x02, 0x0deb8}}, 0x3, 0x0},
|
||||
{0x00,(0x13<<3)|0x0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0x0deb8}}, 0x4, 0x0},
|
||||
{0x00,(0x11<<3)|0x0, {{0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0x0deb8}}, 0x0, 0x0},
|
||||
{0x00,(0x0f<<3)|0x0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0x0deb8}}, 0x0, 0x0},
|
||||
{0x00,(0x01<<3)|0x0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0x0deb8}}, 0x0, 0x0},
|
||||
{0x00,(0x10<<3)|0x0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0x0deb8}}, 0x0, 0x0},
|
||||
{0x00,(0x12<<3)|0x0, {{0x01, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0},
|
||||
}
|
||||
};
|
||||
|
||||
unsigned long write_pirq_routing_table(unsigned long addr)
|
||||
{
|
||||
return copy_pirq_routing_table(addr);
|
||||
}
|
||||
|
|
@ -1,7 +0,0 @@
|
|||
#include <device/device.h>
|
||||
#include "chip.h"
|
||||
|
||||
struct chip_operations mainboard_ops = {
|
||||
CHIP_NAME("Dell S1850 Mainboard")
|
||||
};
|
||||
|
||||
|
|
@ -1,160 +0,0 @@
|
|||
#include <console/console.h>
|
||||
#include <arch/smp/mpspec.h>
|
||||
#include <arch/ioapic.h>
|
||||
#include <device/pci.h>
|
||||
#include <string.h>
|
||||
#include <stdint.h>
|
||||
|
||||
static void *smp_write_config_table(void *v)
|
||||
{
|
||||
struct mp_config_table *mc;
|
||||
int bus_isa;
|
||||
unsigned char bus_pxhd_1;
|
||||
unsigned char bus_pxhd_2;
|
||||
unsigned char bus_pxhd_3;
|
||||
unsigned char bus_pxhd_4;
|
||||
unsigned char bus_ich5r_1;
|
||||
|
||||
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
|
||||
|
||||
mptable_init(mc, LOCAL_APIC_ADDR);
|
||||
|
||||
smp_write_processors(mc);
|
||||
|
||||
{
|
||||
device_t dev;
|
||||
|
||||
/* ich5r */
|
||||
dev = dev_find_slot(0, PCI_DEVFN(0x1e,0));
|
||||
if (dev) {
|
||||
bus_ich5r_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
}
|
||||
else {
|
||||
printk(BIOS_DEBUG, "ERROR - could not find PCI 0:1e.0, using defaults\n");
|
||||
bus_ich5r_1 = 7;
|
||||
}
|
||||
/* pxhd-1 */
|
||||
dev = dev_find_slot(1, PCI_DEVFN(0x0,0));
|
||||
if (dev) {
|
||||
bus_pxhd_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
}
|
||||
else {
|
||||
printk(BIOS_DEBUG, "ERROR - could not find PCI 1:00.0, using defaults\n");
|
||||
bus_pxhd_1 = 2;
|
||||
}
|
||||
/* pxhd-2 */
|
||||
dev = dev_find_slot(1, PCI_DEVFN(0x00,2));
|
||||
if (dev) {
|
||||
bus_pxhd_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
}
|
||||
else {
|
||||
printk(BIOS_DEBUG, "ERROR - could not find PCI 1:00.2, using defaults\n");
|
||||
bus_pxhd_2 = 3;
|
||||
}
|
||||
|
||||
/* pxhd-3 */
|
||||
dev = dev_find_slot(0, PCI_DEVFN(0x4,0));
|
||||
if (dev) {
|
||||
bus_pxhd_3 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
}
|
||||
else {
|
||||
printk(BIOS_DEBUG, "ERROR - could not find PCI 0:04.0, using defaults\n");
|
||||
bus_pxhd_3 = 5;
|
||||
}
|
||||
/* pxhd-4 */
|
||||
dev = dev_find_slot(0, PCI_DEVFN(0x06,0));
|
||||
if (dev) {
|
||||
bus_pxhd_4 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
}
|
||||
else {
|
||||
printk(BIOS_DEBUG, "ERROR - could not find PCI 0:06.0, using defaults\n");
|
||||
bus_pxhd_4 = 6;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
mptable_write_buses(mc, NULL, &bus_isa);
|
||||
|
||||
/* IOAPIC handling */
|
||||
|
||||
smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR);
|
||||
{
|
||||
struct resource *res;
|
||||
device_t dev;
|
||||
/* pxhd apic 3 */
|
||||
dev = dev_find_slot(1, PCI_DEVFN(0x00,1));
|
||||
if (dev) {
|
||||
res = find_resource(dev, PCI_BASE_ADDRESS_0);
|
||||
if (res) {
|
||||
smp_write_ioapic(mc, 0x03, 0x20, res->base);
|
||||
}
|
||||
}
|
||||
else {
|
||||
printk(BIOS_DEBUG, "ERROR - could not find IOAPIC PCI 1:00.1\n");
|
||||
}
|
||||
/* pxhd apic 4 */
|
||||
dev = dev_find_slot(1, PCI_DEVFN(0x00,3));
|
||||
if (dev) {
|
||||
res = find_resource(dev, PCI_BASE_ADDRESS_0);
|
||||
if (res) {
|
||||
smp_write_ioapic(mc, 0x04, 0x20, res->base);
|
||||
}
|
||||
}
|
||||
else {
|
||||
printk(BIOS_DEBUG, "ERROR - could not find IOAPIC PCI 1:00.3\n");
|
||||
}
|
||||
}
|
||||
|
||||
mptable_add_isa_interrupts(mc, bus_isa, 0x2, 0);
|
||||
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
|
||||
0x00, 0x74, 0x02, 0x10);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
|
||||
0x00, 0x76, 0x02, 0x12);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
|
||||
0x00, 0x77, 0x02, 0x17);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
|
||||
0x00, 0x75, 0x02, 0x13);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
|
||||
0x00, 0x74, 0x02, 0x10);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
|
||||
0x00, 0x7c, 0x02, 0x12);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
|
||||
0x00, 0x7d, 0x02, 0x11);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
|
||||
bus_pxhd_1, 0x08, 0x03, 0x00);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
|
||||
bus_pxhd_1, 0x0c, 0x03, 0x06);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
|
||||
bus_pxhd_1, 0x0d, 0x03, 0x07);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
|
||||
bus_pxhd_2, 0x08, 0x04, 0x00);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
|
||||
bus_ich5r_1, 0x04, 0x02, 0x10);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
|
||||
bus_pxhd_4, 0x00, 0x02, 0x10);
|
||||
#if 0
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
|
||||
(bus_isa - 1), 0x04, 0x02, 0x10);
|
||||
#endif
|
||||
/* Standard local interrupt assignments */
|
||||
#if 0
|
||||
smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
|
||||
bus_isa, 0x00, MP_APIC_ALL, 0x00);
|
||||
#endif
|
||||
smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
|
||||
bus_isa, 0x00, MP_APIC_ALL, 0x01);
|
||||
|
||||
/* There is no extension information... */
|
||||
|
||||
/* Compute the checksums */
|
||||
return mptable_finalize(mc);
|
||||
}
|
||||
|
||||
unsigned long write_smp_table(unsigned long addr)
|
||||
{
|
||||
void *v;
|
||||
v = smp_write_floating_table(addr, 0);
|
||||
return (unsigned long)smp_write_config_table(v);
|
||||
}
|
||||
|
||||
|
|
@ -1,16 +0,0 @@
|
|||
#include <arch/io.h>
|
||||
#include <reset.h>
|
||||
#if defined (__PRE_RAM__)
|
||||
#include <arch/romcc_io.h>
|
||||
#endif
|
||||
|
||||
void soft_reset(void)
|
||||
{
|
||||
outb(0x04, 0xcf9);
|
||||
}
|
||||
|
||||
void hard_reset(void)
|
||||
{
|
||||
outb(0x02, 0xcf9);
|
||||
outb(0x06, 0xcf9);
|
||||
}
|
||||
|
|
@ -1,324 +0,0 @@
|
|||
#include <stdint.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <arch/io.h>
|
||||
#include <device/pnp_def.h>
|
||||
#include <arch/romcc_io.h>
|
||||
#include <cpu/x86/lapic.h>
|
||||
#include <stdlib.h>
|
||||
#include <console/console.h>
|
||||
#include "southbridge/intel/i82801ex/early_smbus.c"
|
||||
#include "northbridge/intel/e7520/raminit.h"
|
||||
#include "superio/nsc/pc8374/early_init.c"
|
||||
#include "cpu/x86/lapic/boot_cpu.c"
|
||||
#include "cpu/x86/mtrr/earlymtrr.c"
|
||||
#include "debug.c"
|
||||
#include "watchdog.c"
|
||||
// Remove comment if resets in this file are actually used.
|
||||
// #include "reset.c"
|
||||
#include "s1850_fixups.c"
|
||||
#include "northbridge/intel/e7520/memory_initialized.c"
|
||||
#include "cpu/x86/bist.h"
|
||||
#include <spd.h>
|
||||
|
||||
#define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, PC8374_SP1)
|
||||
|
||||
#define DEVPRES_CONFIG ( \
|
||||
DEVPRES_D0F0 | \
|
||||
DEVPRES_D1F0 | \
|
||||
DEVPRES_D2F0 | \
|
||||
DEVPRES_D3F0 | \
|
||||
DEVPRES_D4F0 | \
|
||||
DEVPRES_D6F0 | \
|
||||
0 )
|
||||
#define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0)
|
||||
|
||||
static inline int spd_read_byte(unsigned device, unsigned address)
|
||||
{
|
||||
return smbus_read_byte(device, address);
|
||||
}
|
||||
|
||||
#include "northbridge/intel/e7520/raminit.c"
|
||||
#include "lib/generic_sdram.c"
|
||||
|
||||
/* IPMI garbage. This is all test stuff, if it really works we'll move it somewhere
|
||||
*/
|
||||
|
||||
#define nftransport 0xc
|
||||
|
||||
#define OBF 0
|
||||
#define IBF 1
|
||||
|
||||
#define ipmidata 0xca0
|
||||
#define ipmicsr 0xca4
|
||||
|
||||
static inline void ibfzero(void)
|
||||
{
|
||||
while(inb(ipmicsr) & (1<<IBF))
|
||||
;
|
||||
}
|
||||
static inline void clearobf(void)
|
||||
{
|
||||
(void) inb(ipmidata);
|
||||
}
|
||||
|
||||
static inline void waitobf(void)
|
||||
{
|
||||
while((inb(ipmicsr) & (1<<OBF)) == 0)
|
||||
;
|
||||
}
|
||||
|
||||
/* quite possibly the stupidest interface ever designed. */
|
||||
static inline void first_cmd_byte(unsigned char byte)
|
||||
{
|
||||
ibfzero();
|
||||
clearobf();
|
||||
outb(0x61, ipmicsr);
|
||||
ibfzero();
|
||||
clearobf();
|
||||
outb(byte, ipmidata);
|
||||
}
|
||||
|
||||
static inline void next_cmd_byte(unsigned char byte)
|
||||
{
|
||||
|
||||
ibfzero();
|
||||
clearobf();
|
||||
outb(byte, ipmidata);
|
||||
}
|
||||
|
||||
static inline void last_cmd_byte(unsigned char byte)
|
||||
{
|
||||
outb(0x62, ipmicsr);
|
||||
|
||||
ibfzero();
|
||||
clearobf();
|
||||
outb(byte, ipmidata);
|
||||
}
|
||||
|
||||
static inline void read_response_byte(void)
|
||||
{
|
||||
int val = -1;
|
||||
if ((inb(ipmicsr)>>6) != 1)
|
||||
return;
|
||||
|
||||
ibfzero();
|
||||
waitobf();
|
||||
val = inb(ipmidata);
|
||||
outb(0x68, ipmidata);
|
||||
|
||||
/* see if it is done */
|
||||
if ((inb(ipmicsr)>>6) != 1){
|
||||
/* wait for the dummy read. Which describes this protocol */
|
||||
waitobf();
|
||||
(void)inb(ipmidata);
|
||||
}
|
||||
}
|
||||
|
||||
static inline void ipmidelay(void)
|
||||
{
|
||||
int i;
|
||||
for(i = 0; i < 1000; i++) {
|
||||
inb(0x80);
|
||||
}
|
||||
}
|
||||
|
||||
static inline void bmc_foad(void)
|
||||
{
|
||||
unsigned char c;
|
||||
/* be safe; make sure it is really ready */
|
||||
while ((inb(ipmicsr)>>6)) {
|
||||
outb(0x60, ipmicsr);
|
||||
inb(ipmidata);
|
||||
}
|
||||
first_cmd_byte(nftransport << 2);
|
||||
ipmidelay();
|
||||
next_cmd_byte(0x12);
|
||||
ipmidelay();
|
||||
next_cmd_byte(2);
|
||||
ipmidelay();
|
||||
last_cmd_byte(3);
|
||||
ipmidelay();
|
||||
}
|
||||
|
||||
/* end IPMI garbage */
|
||||
|
||||
#include "arch/x86/lib/stages.c"
|
||||
|
||||
static void main(unsigned long bist)
|
||||
{
|
||||
u8 b;
|
||||
u16 w;
|
||||
u32 l;
|
||||
int do_reset;
|
||||
|
||||
static const struct mem_controller mch[] = {
|
||||
{
|
||||
.node_id = 0,
|
||||
/* the wiring on this part is really messed up */
|
||||
/* this is my best guess so far */
|
||||
.channel0 = {DIMM0, DIMM1, DIMM2, DIMM3, },
|
||||
.channel1 = {DIMM4, DIMM5, DIMM6, DIMM7, },
|
||||
}
|
||||
};
|
||||
|
||||
/* superio setup */
|
||||
/* observed from serialice */
|
||||
static const u8 earlyinit[] = {
|
||||
0x21, 0x11, 0x11,
|
||||
0x22, 1, 1,
|
||||
0x23, 05, 05,
|
||||
0x24, 0x81, 0x81,
|
||||
0x26, 0, 0,
|
||||
0,
|
||||
};
|
||||
|
||||
/* using SerialICE, we've seen this basic reset sequence on the dell.
|
||||
* we don't understand it as it uses undocumented registers, but
|
||||
* we're going to clone it.
|
||||
*/
|
||||
/* enable a hidden device. */
|
||||
b = pci_read_config8(PCI_DEV(0, 0, 0), 0xf4);
|
||||
b |= 0x8;
|
||||
pci_write_config8(PCI_DEV(0, 0, 0), 0xf4, b);
|
||||
|
||||
/* read-write lock in CMOS on LPC bridge on ICH5 */
|
||||
pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xd8, 4);
|
||||
|
||||
/* operate on undocumented device */
|
||||
l = pci_read_config32(PCI_DEV(0, 0, 2), 0xa4);
|
||||
l |= 0x1000;
|
||||
pci_write_config32(PCI_DEV(0, 0, 2), 0xa4, l);
|
||||
|
||||
l = pci_read_config32(PCI_DEV(0, 0, 2), 0x9c);
|
||||
l |= 0x8000;
|
||||
pci_write_config32(PCI_DEV(0, 0, 2), 0x9c, l);
|
||||
|
||||
/* disable undocumented device */
|
||||
b = pci_read_config8(PCI_DEV(0, 0, 0), 0xf4);
|
||||
b &= ~0x8;
|
||||
pci_write_config8(PCI_DEV(0, 0, 0), 0xf4, b);
|
||||
|
||||
/* set up LPC bridge bits, some of which reply on undocumented
|
||||
* registers
|
||||
*/
|
||||
|
||||
b= pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xd8);
|
||||
b |= 4;
|
||||
pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xd8, b);
|
||||
|
||||
b= pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xd4);
|
||||
b |= 2;
|
||||
pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xd4, b);
|
||||
|
||||
/* ACPI base address */
|
||||
pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x40, 0x800);
|
||||
|
||||
/* Enable specific ACPI features */
|
||||
b= pci_read_config8(PCI_DEV(0, 0x1f, 0), 0x44);
|
||||
b |= 0x10;
|
||||
pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44, b);
|
||||
|
||||
/* ACPI control */
|
||||
w = inw(0x868);
|
||||
outw(w|0x800, 0x868);
|
||||
w = inw(0x866);
|
||||
outw(w|2, 0x866);
|
||||
|
||||
#if 0
|
||||
/*seriaice shows
|
||||
dell does this so leave it here so I don't forget
|
||||
*/
|
||||
/* SMBUS */
|
||||
pci_write_config16(PCI_DEV(0, 0x1f, 3), 0x20, 0x08c0);
|
||||
|
||||
/* unknown */
|
||||
b = inb(0x8c2);
|
||||
outb(0xdf, 0x8c2);
|
||||
#endif
|
||||
|
||||
/* another device enable? */
|
||||
b = pci_read_config8(PCI_DEV(0, 0, 0), 0xf4);
|
||||
b |= 2;
|
||||
pci_write_config8(PCI_DEV(0, 0, 0), 0xf4, b);
|
||||
|
||||
/* ?? */
|
||||
l = pci_read_config32(PCI_DEV(0, 8, 0), 0xc0);
|
||||
do_reset = l & 0x8000000;
|
||||
l |= 0x8000000;
|
||||
pci_write_config32(PCI_DEV(0, 8, 0), 0xc0, l);
|
||||
|
||||
if (! do_reset) {
|
||||
outb(2, 0xcf9);
|
||||
outb(6, 0xcf9);
|
||||
}
|
||||
if (bist == 0) {
|
||||
/* Skip this if there was a built in self test failure */
|
||||
early_mtrr_init();
|
||||
if (memory_initialized())
|
||||
skip_romstage();
|
||||
}
|
||||
/* Setup the console */
|
||||
mainboard_set_ich5();
|
||||
//bmc_foad();
|
||||
pc8374_enable_dev(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE);
|
||||
console_init();
|
||||
|
||||
/* stuff we seem to need */
|
||||
pc8374_enable_dev(PNP_DEV(0x2e, PC8374_KBCK), 0);
|
||||
|
||||
/* GPIOs */
|
||||
pc8374_enable_dev(PNP_DEV(0x2e, PC8374_GPIO), 0xc20);
|
||||
|
||||
/* keep this in mind.
|
||||
SerialICE-hlp: outb 002e <= 23
|
||||
SerialICE-hlp: inb 002f => 05
|
||||
SerialICE-hlp: outb 002f <= 05
|
||||
SerialICE-hlp: outb 002e <= 24
|
||||
SerialICE-hlp: inb 002f => c1
|
||||
SerialICE-hlp: outb 002f <= c1
|
||||
*/
|
||||
|
||||
/* Halt if there was a built in self test failure */
|
||||
// report_bist_failure(bist);
|
||||
|
||||
/* MOVE ME TO A BETTER LOCATION !!! */
|
||||
/* config LPC decode for flash memory access */
|
||||
device_t dev;
|
||||
dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0);
|
||||
if (dev == PCI_DEV_INVALID) {
|
||||
die("Missing ich5?");
|
||||
}
|
||||
pci_write_config32(dev, 0xe8, 0x00000000);
|
||||
pci_write_config8(dev, 0xf0, 0x00);
|
||||
|
||||
#if 0
|
||||
display_cpuid_update_microcode();
|
||||
#endif
|
||||
#if 1
|
||||
print_pci_devices();
|
||||
#endif
|
||||
#if 1
|
||||
enable_smbus();
|
||||
#endif
|
||||
#if 0
|
||||
// dump_spd_registers(&cpu[0]);
|
||||
int i;
|
||||
for(i = 0; i < 1; i++)
|
||||
dump_spd_registers();
|
||||
#endif
|
||||
#if 1
|
||||
show_dram_slots();
|
||||
#endif
|
||||
disable_watchdogs();
|
||||
// dump_ipmi_registers();
|
||||
mainboard_set_e7520_leds();
|
||||
|
||||
sdram_initialize(ARRAY_SIZE(mch), mch);
|
||||
#if 0
|
||||
dump_pci_devices();
|
||||
#endif
|
||||
#if 1
|
||||
dump_pci_device(PCI_DEV(0, 0x00, 0));
|
||||
// dump_bar14(PCI_DEV(0, 0x00, 0));
|
||||
#endif
|
||||
}
|
||||
|
|
@ -1,60 +0,0 @@
|
|||
#include <arch/romcc_io.h>
|
||||
|
||||
static void mch_reset(void)
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
|
||||
|
||||
static void mainboard_set_e7520_pll(unsigned bits)
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
|
||||
static void mainboard_set_e7520_leds(void)
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
static void mainboard_set_ich5(void)
|
||||
{
|
||||
/* coma is 0x3f8 , comb is 0x2f8*/
|
||||
pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xe0, 0x10);
|
||||
/* enable decoding of various devices */
|
||||
pci_write_config16(PCI_DEV(0, 0x1f, 0), 0xe6, 0x140f);
|
||||
/* 1M flash */
|
||||
pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xe3, 0xc0);
|
||||
pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xf0, 0x0);
|
||||
/* disable certain devices -- see data sheet -- this is from
|
||||
* dell settings via lspci
|
||||
* Note that they leave SMBUS disabled -- 8f6f.
|
||||
* we leave it enabled and visible in config space -- 8f66
|
||||
*/
|
||||
pci_write_config16(PCI_DEV(0, 0x1f, 0), 0xf2, 0x8f66);
|
||||
/* GPIOs -- needed, possibly, for SPD */
|
||||
pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x58, 0x881);
|
||||
pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x5c, 0x10);
|
||||
|
||||
/* now the fun begins ... enable the GPIOs as done on factory */
|
||||
/* factory config from IO ports
|
||||
* It has a few more things enabled than default!
|
||||
*/
|
||||
outl(0x1ae0f183, 0x880);
|
||||
outl(0x1b00ffff, 0x884);
|
||||
outl(0x131f0000, 0x88c);
|
||||
outl(0x00000000, 0x894);
|
||||
outl(0x00040000, 0x898);
|
||||
outl(0x00000000, 0x8a4);
|
||||
outl(0x00000000, 0x8a8);
|
||||
outl(0x000031c0, 0x8ac);
|
||||
outl(0x00000007, 0x8b0);
|
||||
outl(0x00000304, 0x8b4);
|
||||
outl(0x00030303, 0x8b8);
|
||||
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
|
|
@ -1,57 +0,0 @@
|
|||
#include <device/pnp_def.h>
|
||||
|
||||
#define NSC_WD_DEV PNP_DEV(0x2e, 0xa)
|
||||
#define NSC_WDBASE 0x600
|
||||
#define ICH5_WDBASE 0x400
|
||||
#define ICH5_GPIOBASE 0x500
|
||||
|
||||
static void disable_sio_watchdog(device_t dev)
|
||||
{
|
||||
#if 0
|
||||
/* FIXME move me somewhere more appropriate */
|
||||
pnp_set_logical_device(dev);
|
||||
pnp_set_enable(dev, 1);
|
||||
pnp_set_iobase(dev, PNP_IDX_IO0, NSC_WDBASE);
|
||||
/* disable the sio watchdog */
|
||||
outb(0, NSC_WDBASE + 0);
|
||||
pnp_set_enable(dev, 0);
|
||||
#endif
|
||||
}
|
||||
|
||||
static void disable_ich5_watchdog(void)
|
||||
{
|
||||
/* FIXME move me somewhere more appropriate */
|
||||
device_t dev;
|
||||
unsigned long value, base;
|
||||
dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0);
|
||||
if (dev == PCI_DEV_INVALID) {
|
||||
die("Missing ich5?");
|
||||
}
|
||||
/* Enable I/O space */
|
||||
value = pci_read_config16(dev, 0x04);
|
||||
value |= (1 << 10);
|
||||
pci_write_config16(dev, 0x04, value);
|
||||
|
||||
/* Set and enable acpibase */
|
||||
pci_write_config32(dev, 0x40, ICH5_WDBASE | 1);
|
||||
pci_write_config8(dev, 0x44, 0x10);
|
||||
base = ICH5_WDBASE + 0x60;
|
||||
|
||||
/* Set bit 11 in TCO1_CNT */
|
||||
value = inw(base + 0x08);
|
||||
value |= 1 << 11;
|
||||
outw(value, base + 0x08);
|
||||
|
||||
/* Clear TCO timeout status */
|
||||
outw(0x0008, base + 0x04);
|
||||
outw(0x0002, base + 0x06);
|
||||
}
|
||||
|
||||
|
||||
static void disable_watchdogs(void)
|
||||
{
|
||||
// disable_sio_watchdog(NSC_WD_DEV);
|
||||
disable_ich5_watchdog();
|
||||
print_debug("Watchdogs disabled\n");
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue