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soc/intel/meteorlake: Use coreboot native event handler for FSP-M/S 

This patch assigns FSP handler event for FSP-M and FSP-S with coreboot
romstage and ramstage debug handler when FSP_USES_CB_DEBUG_EVENT_HANDLER
Kconfig is enabled.

BUG=b:237263080
TEST=Able to build and boot MTL simics. Also, verified the FSP debug
log is using coreboot debug library as below:

Before:

Register PPI Notify: DCD0BE23-9586-40F4-B643-06522CED4EDE
Install PPI: 8C8CE578-8A3D-4F1C-9935-896185C32DD3
Install PPI: 5473C07A-3DCB-4DCA-BD6F-1E9689E7349A
The 0th FV start address is 0x000F961B000, size is 0x00150000, handle
is 0xF961B000
Register PPI Notify: 49EDB1C1-BF21-4761-BB12-EB0031AABB39
Register PPI Notify: EA7CA24B-DED5-4DAD-A389-BF827E8F9B38
Install PPI: B9E0ABFE-5979-4914-977F-6DEE78C278A6

With this code change:

[SPEW ]  Register PPI Notify: DCD0BE23-9586-40F4-B643-06522CED4EDE
[SPEW ]  Install PPI: 8C8CE578-8A3D-4F1C-9935-896185C32DD3
[SPEW ]  Install PPI: 5473C07A-3DCB-4DCA-BD6F-1E9689E7349A
[SPEW ]  The 0th FV start address is 0x000F95C0000, size is 0x00160000, handle is 0xF95C0000
[SPEW ]  Register PPI Notify: 49EDB1C1-BF21-4761-BB12-EB0031AABB39
[SPEW ]  Register PPI Notify: EA7CA24B-DED5-4DAD-A389-BF827E8F9B38
[SPEW ]  Install PPI: B9E0ABFE-5979-4914-977F-6DEE78C278A6

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I80ba73afed642e6d21c5310e9bf734f6f7170347
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65456
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
This commit is contained in:
Subrata Banik 2022-06-27 16:51:44 +05:30
parent 8206741a06
commit e88bee7219
3 changed files with 35 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/soc/intel/meteorlake/Kconfig
View File

@ -15,13 +15,17 @@ config CPU_SPECIFIC_OPTIONS
select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
select CPU_SUPPORTS_INTEL_TME select CPU_SUPPORTS_INTEL_TME
select CPU_SUPPORTS_PM_TIMER_EMULATION select CPU_SUPPORTS_PM_TIMER_EMULATION
select DISPLAY_FSP_VERSION_INFO
select DRIVERS_INTEL_USB4_RETIMER select DRIVERS_INTEL_USB4_RETIMER
select DRIVERS_USB_ACPI select DRIVERS_USB_ACPI
select FSP_COMPRESS_FSP_S_LZ4 select FSP_COMPRESS_FSP_S_LZ4
select FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW select FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW
select FSP_M_XIP select FSP_M_XIP
select FSP_STATUS_GLOBAL_RESET_REQUIRED_3 select FSP_STATUS_GLOBAL_RESET_REQUIRED_3
select FSP_USES_CB_DEBUG_EVENT_HANDLER
select FSPS_HAS_ARCH_UPD
select GENERIC_GPIO_LIB select GENERIC_GPIO_LIB
select HAVE_DEBUG_RAM_SETUP
select HAVE_FSP_GOP select HAVE_FSP_GOP
select INTEL_DESCRIPTOR_MODE_CAPABLE select INTEL_DESCRIPTOR_MODE_CAPABLE
select HAVE_SMI_HANDLER select HAVE_SMI_HANDLER

13
src/soc/intel/meteorlake/fsp_params.c
View File

@ -7,6 +7,7 @@
#include <device/device.h> #include <device/device.h>
#include <device/pci.h> #include <device/pci.h>
#include <fsp/api.h> #include <fsp/api.h>
#include <fsp/fsp_debug_event.h>
#include <fsp/ppi/mp_service_ppi.h> #include <fsp/ppi/mp_service_ppi.h>
#include <fsp/util.h> #include <fsp/util.h>
#include <intelblocks/cse.h> #include <intelblocks/cse.h>
@ -241,6 +242,17 @@ static void fill_fsps_xdci_params(FSP_S_CONFIG *s_cfg,
s_cfg->XdciEnable = xdci_can_enable(PCI_DEVFN_USBOTG); s_cfg->XdciEnable = xdci_can_enable(PCI_DEVFN_USBOTG);
} }
static void fill_fsps_uart_params(FSP_S_CONFIG *s_cfg,
const struct soc_intel_meteorlake_config *config)
{
if (CONFIG(FSP_USES_CB_DEBUG_EVENT_HANDLER) && CONFIG(CONSOLE_SERIAL) &&
CONFIG(FSP_ENABLE_SERIAL_DEBUG))
s_cfg->FspEventHandler = (UINT32)((FSP_EVENT_HANDLER *)
fsp_debug_event_handler);
ASSERT(ARRAY_SIZE(s_cfg->SerialIoUartAutoFlow) > CONFIG_UART_FOR_CONSOLE);
s_cfg->SerialIoUartAutoFlow[CONFIG_UART_FOR_CONSOLE] = 0;
}
static void fill_fsps_sata_params(FSP_S_CONFIG *s_cfg, static void fill_fsps_sata_params(FSP_S_CONFIG *s_cfg,
const struct soc_intel_meteorlake_config *config) const struct soc_intel_meteorlake_config *config)
{ {
@ -423,6 +435,7 @@ static void soc_silicon_init_params(FSP_S_CONFIG *s_cfg,
fill_fsps_chipset_lockdown_params, fill_fsps_chipset_lockdown_params,
fill_fsps_xhci_params, fill_fsps_xhci_params,
fill_fsps_xdci_params, fill_fsps_xdci_params,
fill_fsps_uart_params,
fill_fsps_sata_params, fill_fsps_sata_params,
fill_fsps_thermal_params, fill_fsps_thermal_params,
fill_fsps_lan_params, fill_fsps_lan_params,

18
src/soc/intel/meteorlake/romstage/fsp_params.c
View File

@ -4,6 +4,7 @@
#include <console/console.h> #include <console/console.h>
#include <cpu/x86/msr.h> #include <cpu/x86/msr.h>
#include <device/device.h> #include <device/device.h>
#include <fsp/fsp_debug_event.h>
#include <fsp/util.h> #include <fsp/util.h>
#include <intelblocks/cpulib.h> #include <intelblocks/cpulib.h>
#include <intelblocks/pcie_rp.h> #include <intelblocks/pcie_rp.h>
@ -284,7 +285,24 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
{ {
const struct soc_intel_meteorlake_config *config; const struct soc_intel_meteorlake_config *config;
FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; FSP_M_CONFIG *m_cfg = &mupd->FspmConfig;
FSPM_ARCH_UPD *arch_upd = &mupd->FspmArchUpd;
if (CONFIG(FSP_USES_CB_DEBUG_EVENT_HANDLER)) {
if (CONFIG(CONSOLE_SERIAL) && CONFIG(FSP_ENABLE_SERIAL_DEBUG)) {
enum fsp_log_level log_level = fsp_map_console_log_level();
arch_upd->FspEventHandler = (UINT32)((FSP_EVENT_HANDLER *)
fsp_debug_event_handler);
/* Set Serial debug message level */
m_cfg->PcdSerialDebugLevel = log_level;
/* Set MRC debug level */
m_cfg->SerialDebugMrcLevel = log_level;
} else {
/* Disable Serial debug message */
m_cfg->PcdSerialDebugLevel = 0;
/* Disable MRC debug message */
m_cfg->SerialDebugMrcLevel = 0;
}
}
config = config_of_soc(); config = config_of_soc();
soc_memory_init_params(m_cfg, config); soc_memory_init_params(m_cfg, config);