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Revert "mb/pcengines/apu2: Update GPIO Reads & writes" 

This reverts commit 87f9fc8584.

GPIO configuration is supposed to be abstracted using <gpio.h>
and the details of ACPMMIO GPIO bank hidden. This commit took
it the opposite direction.

Change-Id: Iacd80d1ca24c9d187ff2c8e68e57a609213bad08
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42684
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Kyösti Mälkki 2020-06-22 07:16:27 +03:00 committed by Patrick Georgi
parent 211e74e0f4
commit e8afb0ee92
2 changed files with 8 additions and 11 deletions
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16
src/mainboard/pcengines/apu2/gpio_ftns.c
View File

@ -12,11 +12,11 @@ static u32 gpio_read_wrapper(u32 iomux_gpio)
u32 gpio = iomux_gpio << 2; u32 gpio = iomux_gpio << 2;
if (gpio < 0x100) if (gpio < 0x100)
return read32((void *)(ACPIMMIO_GPIO0_BASE + (gpio & 0xff))); return gpio0_read32(gpio & 0xff);
else if (gpio >= 0x100 && gpio < 0x200) else if (gpio >= 0x100 && gpio < 0x200)
return read32((void *)(ACPIMMIO_GPIO1_BASE + (gpio & 0xff))); return gpio1_read32(gpio & 0xff);
else if (gpio >= 0x200 && gpio < 0x300) else if (gpio >= 0x200 && gpio < 0x300)
return read32((void *)(ACPIMMIO_GPIO2_BASE + (gpio & 0xff))); return gpio2_read32(gpio & 0xff);
die("Invalid GPIO"); die("Invalid GPIO");
} }
@ -26,11 +26,11 @@ static void gpio_write_wrapper(u32 iomux_gpio, u32 setting)
u32 gpio = iomux_gpio << 2; u32 gpio = iomux_gpio << 2;
if (gpio < 0x100) if (gpio < 0x100)
write32((void *)(ACPIMMIO_GPIO0_BASE + (gpio & 0xff)), setting); gpio0_write32(gpio & 0xff, setting);
else if (gpio >= 0x100 && gpio < 0x200) else if (gpio >= 0x100 && gpio < 0x200)
write32((void *)(ACPIMMIO_GPIO1_BASE + (gpio & 0xff)), setting); gpio1_write32(gpio & 0xff, setting);
else if (gpio >= 0x200 && gpio < 0x300) else if (gpio >= 0x200 && gpio < 0x300)
write32((void *)(ACPIMMIO_GPIO2_BASE + (gpio & 0xff)), setting); gpio2_write32(gpio & 0xff, setting);
} }
void configure_gpio(u32 gpio, u8 iomux_ftn, u32 setting) void configure_gpio(u32 gpio, u8 iomux_ftn, u32 setting)
@ -70,9 +70,9 @@ int get_spd_offset(void)
* One SPD file contains all 4 options, determine which index to * One SPD file contains all 4 options, determine which index to
* read here, then call into the standard routines. * read here, then call into the standard routines.
*/ */
if (read32((void *)(ACPIMMIO_GPIO1_BASE + 0x02)) & BIT0) if (gpio1_read8(0x02) & BIT0)
index |= BIT0; index |= BIT0;
if (read32((void *)(ACPIMMIO_GPIO1_BASE + 0x06)) & BIT0) if (gpio1_read8(0x06) & BIT0)
index |= BIT1; index |= BIT1;
return index; return index;

3
src/mainboard/pcengines/apu2/gpio_ftns.h
View File

@ -8,9 +8,6 @@ u8 read_gpio(u32 gpio);
void write_gpio(u32 gpio, u8 value); void write_gpio(u32 gpio, u8 value);
int get_spd_offset(void); int get_spd_offset(void);
#define ACPIMMIO_GPIO0_BASE 0xfed81500
#define ACPIMMIO_GPIO1_BASE 0xfed81600
#define ACPIMMIO_GPIO2_BASE 0xfed81700
// //
// Based on PC Engines APU2C and APU3A schematics // Based on PC Engines APU2C and APU3A schematics
// http://www.pcengines.ch/schema/apu2c.pdf // http://www.pcengines.ch/schema/apu2c.pdf