Documentation/releases: Update 4.16 release notes
Update details for upcoming 4.16 release Change-Id: Iea88b3a4025ae6a57524e08bf5ecef984810baeb Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62302 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
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Jason Glenesk
Martin Roth
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Upcoming release - coreboot 4.16
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coreboot 4.16
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================================
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The 4.16 release is planned for February, 2022.
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The 4.16 release is planned for February 25th, 2022.
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We are increasing the frequency of releases in order to enable others to release quarterly on
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a fresher version of coreboot.
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Since 4.15 there have been more than 1730 new commits by more than 171 developers.
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Of these, over 35 contributed to coreboot for the first time.
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Update this document with changes that should be in the release notes.
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Welcome to the project!
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* Please use Markdown.
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* See the past few release notes for the general format.
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* The chip and board additions and removals will be updated right
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before the release, so those do not need to be added.
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Thank you to all the developers who continue to make coreboot the
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great open source firmware project that it is.
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New mainboards:
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-------------------
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* Acer Aspire VN7-572G
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* AMD Chausie
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* ASROCK H77 Pro4-M
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* ASUS P8Z77-M
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* Emulation QEMU power9
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* Google -> Agah
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* Google -> Anahera4ES
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* Google -> Banshee
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* Google -> Beadrix
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* Google -> Brya4ES
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* Google -> Crota
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* Google -> Dojo
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* Google -> Gimble4ES
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* Google -> Herobrine_Rev0
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* Google -> Kingler
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* Google -> Kinox
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* Google -> Krabby
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* Google -> Moli
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* Google -> Nereid
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* Google -> Nivviks
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* Google -> Primus4ES
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* Google -> Redrix4ES
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* Google -> Skyrim
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* Google -> Taeko4ES
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* Google -> Taniks
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* Google -> Vell
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* Google -> Volmar
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* Intel Alderlake-N RVP
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* Prodrive Atlas
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* Star Labs Star Labs StarBook Mk V (i3-1115G4 and i7-1165G7)
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* System76 gaze16 3050
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* System76 gaze16 3060
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* System76 gaze16 3060-b
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Removed mainboards:
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-------------------
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* Google -> Corsola
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* Google -> Nasher
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* Google -> Stryke
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Added processors:
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-------------------
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* src/cpu/power9
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Submodule Updates
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-----------------
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/3rdparty/amd_blobs (6 commits)
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/3rdparty/arm-trusted-firmware (965 commits)
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/3rdparty/blobs (30 commits)
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/3rdparty/chromeec (2212 commits)
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/3rdparty/intel-microcode (1 commits)
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/3rdparty/qc_blobs (13 commits)
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/3rdparty/vboot (44 commits)
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Deprecations and incompatible changes
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-------------------------------------
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Significant changes
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-------------------
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@ -19,9 +77,214 @@ Significant changes
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### Add significant changes here
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### Option to disable Intel Management Engine
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Disable the Intel (Converged Security) Management Engine ((CS)ME) via HECI based
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on Intel Core processors from Skylake to Alder Lake. State is set based on a
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CMOS value of `me_state`. A value of `0` will result in a (CS)ME state of `0`
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(working) and value of `1` will result in a (CS)ME state of `3` (disabled). For
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an example CMOS layout and more info, see
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[cse.c](../../src/soc/intel/common/block/cse/cse.c).
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### Add [AMD] apcb_v3_edit tool
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apcb_v3_edit.py tool edits APCB V3 binaries. Specifically it will inject
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up to 16 SPDs into an existing APCB. The APCB must have a magic number
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at the top of each SPD slot.
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### Allow enable/disable ME via CMOS
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Add .enable method that will set the CSME state. The state is based on
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the new CMOS option me_state, with values of 0 and 1. The method is very
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stable when switching between different firmware platforms.
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This method should not be used in combination with USE_ME_CLEANER.
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State 1 will result in:
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ME: Current Working State : 4
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ME: Current Operation State : 1
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ME: Current Operation Mode : 3
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ME: Error Code : 2
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State 0 will result in:
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ME: Current Working State : 5
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ME: Current Operation State : 1
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ME: Current Operation Mode : 0
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ME: Error Code : 0
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### Move LAPIC configuration to MP init
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Implementation for setup_lapic() did two things -- call
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enable_lapic() and virtual_wire_mode_init().
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In PARALLEL_MP case enable_lapic() was redundant as it
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was already executed prior to initialize_cpu() call.
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For the !PARALLEL_MP case enable_lapic() is added to
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AP CPUs.
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### Add ANSI escape sequences for highlighting
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This patch adds ANSI escape sequences to highlight a log line based on
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its loglevel to the output of "interactive" consoles that are meant to
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be displayed on a terminal (e.g. UART). This should help make errors and
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warnings stand out better among the usual spew of debug messages. For
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users whose terminal or use case doesn't support these sequences for
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some reason (or who simply don't like them), they can be disabled with a
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Kconfig.
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While ANSI escape sequences can be used to add color, minicom (the
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presumably most common terminal emulator for UART endpoints?) doesn't
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support color output unless explicitly enabled (via -c command line
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flag), and other terminal emulators may have similar restrictions, so in
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an effort to make this as widely useful by default as possible I have
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chosen not to use color codes and implement this highlighting via
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bolding, underlining and inverting alone (which seem to go through in
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all cases). If desired, support for separate color highlighting could be
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added via Kconfig later.
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### Add cbmem_dump_console
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This function is similar to cbmem_dump_console_to_uart except it uses
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the normally configured consoles. A console_paused flag was added to
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prevent the cbmem console from writing to itself.
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### Add coreboot-configurator
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A simple GUI to change settings in coreboot's CBFS, via the nvramtool utility.
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### Update to NixOS 21.11
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Update configs so that they work with NixOS 21.11. Drop `iasl` package
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since it was replaced with `acpica-tools`.
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### Move to v2021.10
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Move to building the latest U-Boot.
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### Support systems with >128 cores
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Each time the spinlock is acquired a byte is decreased and then the
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sign of the byte is checked. If there are more than 128 cores the sign
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check will overflow. An easy fix is to increase the word size of the
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spinlock acquiring and releasing.
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### Add [samsung] sx9360 [proximity sensor] driver
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Add driver for setting up Semtech sx9360 SAR sensor.
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The driver is based on sx9310.c. The core of the driver is the same, but
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the bindings are slightly different.
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Registers are documented in the kernel tree:
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Documentation/devicetree/bindings/iio/proximity/semtech,sx9360.yaml
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[https://patchwork.kernel.org/project/linux-iio/patch/20211213024057.3824985-4-gwendal@chromium.org/]
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### Add driver for Genesys Logic [SD Controller] GL9750
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The device is a PCIe Gen1 to SD 3.0 card reader controller to be
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used in the Chromebook. The datasheet name is GL9750S and the revision
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is 01.
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The patch disables ASPM L0s.
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### Add support for Realtek RT8125
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The Realtek RT8168 and RT8125 have a similar programming interface,
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therefore add the PCI device ID for the RT8125 into driver for support.
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### Add Fibocom 5G WWAN ACPI support
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Support PXSX._RST and PXSX.MRST._RST for warm and cold reset.
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PXSX._RST is invoked on driver removal.
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build dependency:
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soc/intel/common/block/pcie/rtd3
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This driver will use the rtd3 methods for the same parent in the device
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tree. The rtd3 chip needs to be added on the same root port in the
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devicetree separately.
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### Fix bug in vr_config
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The `cpu_get_power_max()` function returns the TDP in milliwatts, but
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the vr_config code interprets the value in watts. Divide the value by
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1000 to fix this.
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This also fixes an integer overflow when `cpu_get_power_max()` returns
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a value greater than 65535 (UINT16_MAX).
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### Make mixed topo work
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When using a mixed memory topology with DDR4, it's not possible to boot
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when no DIMMs are installed, even though memory-down is available. This
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happens because the DIMM SPD length defaults to 256 when no DIMM SPD is
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available. Relax the length check when no DIMMs are present to overcome
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this problem.
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### Add FSP 2.3 support
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FSP 2.3 specification introduces following changes:
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1. FSP_INFO_HEADER changes
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Updated SpecVersion from 0x22 to 0x23
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Updated HeaderRevision from 5 to 6
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Added ExtendedImageRevision
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FSP_INFO_HEADER length changed to 0x50
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2. Added FSP_NON_VOLATILE_STORAGE_HOB2
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Following changes are implemented in the patch to support FSP 2.3:
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- Add Kconfig option
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- Update FSP build binary version info based on ExtendedImageRevision
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field in header
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- New NV HOB related changes will be pushed as part of another patch
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### Join hash calculation for verification and measurement
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This patch moves the CBFS file measurement when CONFIG_TPM_MEASURED_BOOT
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is enabled from the lookup step into the code where a file is actually
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loaded or mapped from flash. This has the advantage that CBFS routines
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which just look up a file to inspect its metadata (e.g. cbfs_get_size())
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do not cause the file to be measured twice. It also removes the existing
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inefficiency that files are loaded twice when measurement is enabled
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(once to measure and then again when they are used). When CBFS
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verification is enabled and uses the same hash algorithm as the TPM, we
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are even able to only hash the file a single time and use the result for
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both purposes.
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### Skip FSP Notify APIs
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Alder Lake SoC deselects Kconfigs as below:
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- USE_FSP_NOTIFY_PHASE_READY_TO_BOOT
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- USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE
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to skip FSP notify APIs (Ready to boot and End of Firmware) and make
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use of native coreboot driver to perform SoC recommended operations
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prior booting to payload/OS.
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Additionally, created a helper function `heci_finalize()` to keep HECI
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related operations separated for easy guarding again config.
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TODO: coreboot native implementation to skip FSP notify phase API (post
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pci enumeration) is still WIP.
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### Add support for PCIe Resizable BARs
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Section 7.8.6 of the PCIe spec (rev 4) indicates that some devices can
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indicates support for "Resizable BARs" via a PCIe extended capability.
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When support this capability is indicated by the device, the size of
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each BAR is determined in a different way than the normal "moving
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bits" method. Instead, a pair of capability and control registers is
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allocated in config space for each BAR, which can be used to both
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indicate the different sizes the device is capable of supporting for
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the BAR (powers-of-2 number of bits from 20 [1 MiB] to 63 [8 EiB]), and
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to also inform the device of the size that the allocator actually
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reserved for the MMIO range.
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This patch adds a Kconfig for a mainboard to select if it knows that it
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will have a device that requires this support during PCI enumeration.
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If so, there is a corresponding Kconfig to indicate the maximum number
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of bits of address space to hand out to devices this way (again, limited
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by what devices can support and each individual system may want to
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support, but just like above, this number can range from 20 to 63) If
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the device can support more bits than this Kconfig, the resource request
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is truncated to the number indicated by this Kconfig.
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