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jasperlake: update processor power limits configuration 

Update processor power limit configuration parameters based on
common code base support for Intel Jasperlake SoC based platforms.

BRANCH=None
BUG=None
TEST=Built for jasperlake system

Change-Id: I9b725d041dcb8847f83ec103e58b9571b4c596ac
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41237
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Sumeet R Pawnikar 2020-05-08 21:31:44 +05:30 committed by Patrick Georgi
parent 4fafd41209
commit e8d1bef8cb
3 changed files with 6 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/soc/intel/jasperlake/Kconfig
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@ -16,6 +16,7 @@ config CPU_SPECIFIC_OPTIONS
select BOOT_DEVICE_SUPPORTS_WRITES select BOOT_DEVICE_SUPPORTS_WRITES
select CACHE_MRC_SETTINGS select CACHE_MRC_SETTINGS
select COMMON_FADT select COMMON_FADT
select CPU_INTEL_COMMON
select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
select FSP_M_XIP select FSP_M_XIP
select GENERIC_GPIO_LIB select GENERIC_GPIO_LIB
@ -50,6 +51,7 @@ config CPU_SPECIFIC_OPTIONS
select SOC_INTEL_COMMON_BLOCK_SA select SOC_INTEL_COMMON_BLOCK_SA
select SOC_INTEL_COMMON_BLOCK_SCS select SOC_INTEL_COMMON_BLOCK_SCS
select SOC_INTEL_COMMON_BLOCK_SMM select SOC_INTEL_COMMON_BLOCK_SMM
select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT
select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP
select SOC_INTEL_COMMON_PCH_BASE select SOC_INTEL_COMMON_PCH_BASE
select SOC_INTEL_COMMON_RESET select SOC_INTEL_COMMON_RESET

6
src/soc/intel/jasperlake/chip.h
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@ -7,6 +7,7 @@
#include <intelblocks/cfg.h> #include <intelblocks/cfg.h>
#include <intelblocks/gpio.h> #include <intelblocks/gpio.h>
#include <intelblocks/gspi.h> #include <intelblocks/gspi.h>
#include <intelblocks/power_limit.h>
#include <soc/gpe.h> #include <soc/gpe.h>
#include <soc/gpio.h> #include <soc/gpio.h>
#include <soc/gpio_defs.h> #include <soc/gpio_defs.h>
@ -26,6 +27,9 @@ struct soc_intel_jasperlake_config {
/* Common struct containing soc config data required by common code */ /* Common struct containing soc config data required by common code */
struct soc_intel_common_config common_soc_config; struct soc_intel_common_config common_soc_config;
/* Common struct containing power limits configuration information */
struct soc_power_limits_config power_limits_config;
/* Gpio group routed to each dword of the GPE0 block. Values are /* Gpio group routed to each dword of the GPE0 block. Values are
* of the form PMC_GPP_[A:U] or GPD. */ * of the form PMC_GPP_[A:U] or GPD. */
uint8_t pmc_gpe0_dw0; /* GPE0_31_0 STS/EN */ uint8_t pmc_gpe0_dw0; /* GPE0_31_0 STS/EN */
@ -145,8 +149,6 @@ struct soc_intel_jasperlake_config {
/* HeciEnabled decides the state of Heci1 at end of boot /* HeciEnabled decides the state of Heci1 at end of boot
* Setting to 0 (default) disables Heci1 and hides the device from OS */ * Setting to 0 (default) disables Heci1 and hides the device from OS */
uint8_t HeciEnabled; uint8_t HeciEnabled;
/* PL2 Override value in Watts */
uint32_t tdp_pl2_override;
/* Intel Speed Shift Technology */ /* Intel Speed Shift Technology */
uint8_t speed_shift_enable; uint8_t speed_shift_enable;

3
src/soc/intel/jasperlake/include/soc/cpu.h
View File

@ -30,7 +30,4 @@
C_STATE_LATENCY_MICRO_SECONDS(C_STATE_LATENCY_CONTROL_ ##reg## _LIMIT, \ C_STATE_LATENCY_MICRO_SECONDS(C_STATE_LATENCY_CONTROL_ ##reg## _LIMIT, \
(IRTL_1024_NS >> 10)) (IRTL_1024_NS >> 10))
/* Configure power limits for turbo mode */
void set_power_limits(u8 power_limit_1_time);
#endif #endif