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soc/amd/common,stoneyridge: drop invalid hda_soc_ssdt_quirks 

Drop the hda_soc_ssdt_quirks function since it doesn't apply for any of
the SoCs supported by the Stoneyridge code which was the only SoC
implementing it. This code was added when commit 91a7abf25c
("soc/amd/hda: Move HDA PCI device from DSDT to SSDT") rewrote the code
originally added in commit 1587dc8a2b ("soc/amd/stoneyridge: Add
northbridge support") as a copy from northbridge/amd/pi/00670F00. This
code was moved around in commit 6580408a7e ("amd/pi/hudson: Move audio
to northbridge"), since the HDA controller was moved from the FCH to the
northbridge complex. When the controller was moved, the PCI config space
interface also changed, so those bits are no longer the DisableNoSnoop,
DisableNoSnoopOverride, and EnableNoSnoopRequest bits of the Misc
Control register of the HDA controller, but some bits within the
ClassCodeW field of the ACGAZ Mirrot Reg Ctrl 0 register.

BKDG #55072 Rev 3.04 (Stoneyridge), BKDG #50742 Rev 3.08 (family 15h
model 60h-6fh / 00670F00), and BKDG #52740 Rev 3.05 (family 16h model
30h-3fh) were used as a reference. Only the SoC with BKDG #52740 still
has the HDA controller in the FCH; the other two have it in the
northbridge.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I77fc76752b1c7de62ba8a196f15c198f55be3074
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78940
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Felix Held 2023-11-06 19:23:40 +01:00
parent a49e7b974d
commit e91785dfd8
3 changed files with 1 additions and 70 deletions
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13
src/soc/amd/common/block/hda/hda.c
View File

@ -1,7 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */
#include <acpi/acpigen.h> #include <acpi/acpigen.h>
#include <amdblocks/hda.h>
#include <device/device.h> #include <device/device.h>
#include <device/pci.h> #include <device/pci.h>
#include <device/pci_ids.h> #include <device/pci_ids.h>
@ -20,23 +19,13 @@ static const char *hda_acpi_name(const struct device *dev)
return "AZHD"; return "AZHD";
} }
__weak void hda_soc_ssdt_quirks(const struct device *dev)
{
}
static void hda_fill_ssdt(const struct device *dev)
{
acpi_device_write_pci_dev(dev);
hda_soc_ssdt_quirks(dev);
}
static struct device_operations hda_audio_ops = { static struct device_operations hda_audio_ops = {
.read_resources = pci_dev_read_resources, .read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources, .set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources, .enable_resources = pci_dev_enable_resources,
.ops_pci = &pci_dev_ops_pci, .ops_pci = &pci_dev_ops_pci,
.acpi_name = hda_acpi_name, .acpi_name = hda_acpi_name,
.acpi_fill_ssdt = hda_fill_ssdt, .acpi_fill_ssdt = acpi_device_write_pci_dev,
}; };
static const struct pci_driver hdaaudio_driver __pci_driver = { static const struct pci_driver hdaaudio_driver __pci_driver = {

11
src/soc/amd/common/block/include/amdblocks/hda.h
View File

@ -1,11 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef AMD_BLOCK_HDA_H
#define AMD_BLOCK_HDA_H
#include <device/device.h>
/* SoC callback to add any quirks to HDA device node in SSDT. */
void hda_soc_ssdt_quirks(const struct device *dev);
#endif /* AMD_BLOCK_HDA_H */

47
src/soc/amd/stoneyridge/northbridge.c
View File

@ -3,7 +3,6 @@
#include <assert.h> #include <assert.h>
#include <amdblocks/acpi.h> #include <amdblocks/acpi.h>
#include <amdblocks/biosram.h> #include <amdblocks/biosram.h>
#include <amdblocks/hda.h>
#include <device/pci_ops.h> #include <device/pci_ops.h>
#include <arch/hpet.h> #include <arch/hpet.h>
#include <arch/ioapic.h> #include <arch/ioapic.h>
@ -408,49 +407,3 @@ void SetNbMidParams(GNB_MID_CONFIGURATION *params)
params->iGpuVgaMode = 0; params->iGpuVgaMode = 0;
params->GnbIoapicAddress = IO_APIC2_ADDR; params->GnbIoapicAddress = IO_APIC2_ADDR;
} }
void hda_soc_ssdt_quirks(const struct device *dev)
{
const char *scope = acpi_device_path(dev);
static const struct fieldlist list[] = {
FIELDLIST_OFFSET(0x42),
FIELDLIST_NAMESTR("NSDI", 1),
FIELDLIST_NAMESTR("NSDO", 1),
FIELDLIST_NAMESTR("NSEN", 1),
};
struct opregion opreg = OPREGION("AZPD", PCI_CONFIG, 0x0, 0x100);
assert(scope);
acpigen_write_scope(scope);
/*
* OperationRegion(AZPD, PCI_Config, 0x00, 0x100)
* Field (AZPD, AnyAcc, NoLock, Preserve) {
* Offset (0x42),
* NSDI, 1,
* NSDO, 1,
* NSEN, 1,
* }
*/
acpigen_write_opregion(&opreg);
acpigen_write_field(opreg.name, list, ARRAY_SIZE(list),
FIELD_ANYACC | FIELD_NOLOCK | FIELD_PRESERVE);
/*
* Method (_INI, 0, NotSerialized) {
* Store (Zero, NSEN)
* Store (One, NSDO)
* Store (One, NSDI)
* }
*/
acpigen_write_method("_INI", 0);
acpigen_write_store_op_to_namestr(ZERO_OP, "NSEN");
acpigen_write_store_op_to_namestr(ONE_OP, "NSDO");
acpigen_write_store_op_to_namestr(ONE_OP, "NSDI");
acpigen_pop_len(); /* Method _INI */
acpigen_pop_len(); /* Scope */
}