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Documentation: x86 shadow ROM disable 

Add documentation on disabling the SPI flash which is mapped (shadowed)
into the x86 address space at 0x000e0000 - 0x000fffff.

TEST=None

Change-Id: I1d94d84c6cade97886a3274a7e7403f7b3275c5a
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/14112
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Lee Leahy 2016-01-31 11:28:06 -08:00 committed by Martin Roth
parent d75ed0bfd9
commit e9a6d1a813
2 changed files with 24 additions and 2 deletions
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14
Documentation/Intel/SoC/soc.html
View File

@ -24,6 +24,7 @@
<li>Enable <a href="#SerialOutput">Serial Output"</a></li> <li>Enable <a href="#SerialOutput">Serial Output"</a></li>
<li>Get the <a href="#PreviousSleepState">Previous Sleep State</a></li> <li>Get the <a href="#PreviousSleepState">Previous Sleep State</a></li>
<li>Add the <a href="#MemoryInit">MemoryInit</a> Support</li> <li>Add the <a href="#MemoryInit">MemoryInit</a> Support</li>
<li>Disable the <a href="#DisableShadowRom">Shadow ROM</a></li>
</ol> </ol>
</li> </li>
<li><a href="#Ramstage">Ramstage</a> <li><a href="#Ramstage">Ramstage</a>
@ -389,6 +390,17 @@ Use the following steps to debug the call to TempRamInit:
</ol> </ol>
<h2><a name="DisableShadowRom">Disable Shadow ROM</a></h2>
<p>
A shadow of the SPI flash part is mapped from 0x000e0000 to 0x000fffff.
This shadow needs to be disabled to allow RAM to properly respond to
this address range.
</p>
<ol>
<li>Edit romstage/romstage.c and add the soc_after_ram_init routine</li>
</ol>
<hr> <hr>
<h1><a name="Ramstage">Ramstage</a></h1> <h1><a name="Ramstage">Ramstage</a></h1>
@ -717,6 +729,6 @@ Use the following steps to debug the call to TempRamInit:
</table> </table>
<hr> <hr>
<p>Modified: 28 February 2016</p> <p>Modified: 4 March 2016</p>
</body> </body>
</html> </html>

12
Documentation/Intel/development.html
View File

@ -94,6 +94,9 @@
</li> </li>
</ol> </ol>
</li> </li>
<li>Disable the
<a target="_blank" href="SoC/soc.html#DisableShadowRom">Shadow ROM</a>
</li>
<li> <li>
Implement the .init routine for the Implement the .init routine for the
<a target="_blank" href="SoC/soc.html#ChipOperations">chip operations</a> <a target="_blank" href="SoC/soc.html#ChipOperations">chip operations</a>
@ -198,6 +201,13 @@
for the PCI devices on the bus. for the PCI devices on the bus.
</td> </td>
</tr> </tr>
<tr>
<td>ROM Shadow<br>0x000E0000 - 0x000FFFFF</td>
<td>
Disable: src/soc/&lt;Vendor&gt;/&lt;Chip Family&gt;/romstage/romstage.c/<a target="_blank" href="SoC/soc.html#DisableShadowRom">soc_after_ram_init routine</a>
</td>
<td>Operates as RAM: Writes followed by a read to the 0x000E0000 - 0x000FFFFF region returns the value written</td>
</tr>
<tr bgcolor="#c0ffc0"> <tr bgcolor="#c0ffc0">
@ -346,6 +356,6 @@
<hr> <hr>
<p>Modified: 24 February 2016</p> <p>Modified: 4 March 2016</p>
</body> </body>
</html> </html>