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soc/amd/stoneyridge/fch: add GNVS-related TODOs 

The AOAC device states shouldn't be stored in GNVS, but be read from the
AOAC registers during runtime. Same for the EHCI controller's BAR0. The
location and size of the XHCI firmware can either be statically
determined at build-time or have coreboot generate ACPI objects that
contain the needed addresses. Since I can't easily test changes that
require booting to a desktop on Stoneyridge at the moment, only add
TODOs for now.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Suggested-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Change-Id: I3691b05606b9430cb60923780a6131993a9887d4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60196
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This commit is contained in:
Felix Held 2021-12-15 20:52:10 +01:00
parent 2d020e1cc3
commit ea6ee07f43
1 changed files with 2 additions and 0 deletions
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src/soc/amd/stoneyridge/fch.c
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@ -165,12 +165,14 @@ static void set_sb_gnvs(struct global_nvs *gnvs)
gnvs->fw02 = fwaddr + XHCI_FW_BOOTRAM_SIZE;
gnvs->fw03 = fwsize << 16;
/* TODO: This might break if the OS decides to re-allocate the PCI BARs. */
gnvs->eh10 = pci_read_config32(SOC_EHCI1_DEV, PCI_BASE_ADDRESS_0)
& ~PCI_BASE_ADDRESS_MEM_ATTR_MASK;
}
void fch_final(void *chip_info)
{
/* TODO: The AOAC states and EHCI/XHCI addresses should be moved out of GNVS */
struct global_nvs *gnvs = acpi_get_gnvs();
if (gnvs) {
set_sb_aoac(&gnvs->aoac);