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use the standard udelay on sc520. 

Acked-by: Stefan Reinauer <stepan@coresystems.de>
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5418 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Stefan Reinauer 2010-04-13 10:04:35 +00:00 committed by Stefan Reinauer
parent f17ca16624
commit ea7f5a253b
2 changed files with 4 additions and 28 deletions
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19
src/cpu/amd/sc520/raminit.c
View File

@ -234,18 +234,7 @@ dummy_write(void){
*ptr = 0;
}
void sc520_udelay(int microseconds) {
volatile int x;
for(x = 0; x < 1000; x++)
;
}
/* looks like we define this now */
void
udelay(int microseconds) {
sc520_udelay(microseconds);
}
#include "pc80/udelay_io.c"
static void dumpram(void){
print_err("ctl "); print_err_hex8(*drcctl); print_err("\n");
@ -311,7 +300,7 @@ int sizemem(void)
print_err("NOP\n");
/* 100? 200? */
udelay(100);
print_err("after sc520_udelay\n");
print_err("after udelay\n");
/* issue all banks precharge */
*drcctl=0x02;
@ -385,8 +374,8 @@ int sizemem(void)
dummy_write();
print_err("NOP\n");
/* 100? 200? */
//sc520_udelay(100);
print_err("after sc520_udelay\n");
//udelay(100);
print_err("after udelay\n");
/* issue all banks precharge */
*drcctl=0x02;

13
src/cpu/amd/sc520/sc520.c
View File

@ -15,19 +15,6 @@
#include <delay.h>
#include "chip.h"
/* hack for now */
static void sc520_udelay(int microseconds) {
volatile int x;
for(x = 0; x < 1000; x++)
;
}
/* looks like we define this now */
void
udelay(unsigned microseconds) {
sc520_udelay(microseconds);
}
/*
* set up basic things ...
* PAR should NOT go here, as it might change with the mainboard.